Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/interconnect/qcom,osm-l3.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Qualcomm Operating State Manager (OSM) L3 Interconnect Provider
   8
   9 maintainers:
  10   - Sibi Sankar <sibis@codeaurora.org>
  11
  12 description:
  13   L3 cache bandwidth requirements on Qualcomm SoCs is serviced by the OSM.
  14   The OSM L3 interconnect provider aggregates the L3 bandwidth requests
  15   from CPU/GPU and relays it to the OSM.
  16
  17 properties:
  18   compatible:
  19     enum:
  20       - qcom,sc7180-osm-l3
  21       - qcom,sdm845-osm-l3
  22
  23   reg:
  24     maxItems: 1
  25
  26   clocks:
  27     items:
  28       - description: xo clock
  29       - description: alternate clock
  30
  31   clock-names:
  32     items:
  33       - const: xo
  34       - const: alternate
  35
  36   '#interconnect-cells':
  37     const: 1
  38
  39 required:
  40   - compatible
  41   - reg
  42   - clocks
  43   - clock-names
  44   - '#interconnect-cells'
  45
  46 additionalProperties: false
  47
  48 examples:
  49   - |
  50
  51     #define GPLL0               165
  52     #define RPMH_CXO_CLK        0
  53
  54     osm_l3: interconnect@17d41000 {
  55       compatible = "qcom,sdm845-osm-l3";
  56       reg = <0x17d41000 0x1400>;
  57
  58       clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
  59       clock-names = "xo", "alternate";
  60
  61       #interconnect-cells = <1>;
  62     };