1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/i2c/renesas,riic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas RZ/A and RZ/G2L I2C Bus Interface (RIIC)
10 - Chris Brandt <chris.brandt@renesas.com>
11 - Wolfram Sang <wsa+renesas@sang-engineering.com>
14 - $ref: /schemas/i2c/i2c-controller.yaml#
20 - renesas,riic-r7s72100 # RZ/A1H
21 - renesas,riic-r7s9210 # RZ/A2M
22 - renesas,riic-r9a07g044 # RZ/G2{L,LC}
23 - const: renesas,riic-rz # RZ/A or RZ/G2L
30 - description: Transmit End Interrupt
31 - description: Receive Data Full Interrupt
32 - description: Transmit Data Empty Interrupt
33 - description: Stop Condition Detection Interrupt
34 - description: Start Condition Detection Interrupt
35 - description: NACK Reception Interrupt
36 - description: Arbitration-Lost Interrupt
37 - description: Timeout Interrupt
52 Desired I2C bus clock frequency in Hz. The absence of this property
53 indicates the default frequency 100 kHz.
77 - renesas,riic-r9a07g044
82 unevaluatedProperties: false
86 #include <dt-bindings/clock/r7s72100-clock.h>
87 #include <dt-bindings/interrupt-controller/arm-gic.h>
90 compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
91 reg = <0xfcfee000 0x44>;
92 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
93 <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>,
94 <GIC_SPI 159 IRQ_TYPE_EDGE_RISING>,
95 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
96 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
97 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
98 <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
99 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
100 interrupt-names = "tei", "ri", "ti", "spi", "sti", "naki", "ali",
102 clocks = <&mstp9_clks R7S72100_CLK_I2C0>;
103 clock-frequency = <100000>;
104 power-domains = <&cpg_clocks>;
105 #address-cells = <1>;