1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/firmware/xilinx/xlnx,zynqmp-firmware.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx firmware driver
10 - Nava kishore Manne <nava.kishore.manne@amd.com>
12 description: The zynqmp-firmware node describes the interface to platform
13 firmware. ZynqMP has an interface to communicate with secure firmware.
14 Firmware driver provides an interface to firmware APIs. Interface APIs
15 can be used by any driver to communicate to PMUFW(Platform Management Unit).
16 These requests include clock management, pin control, device control,
17 power management service, FPGA service and other platform management
23 - description: For implementations complying for Zynq Ultrascale+ MPSoC.
24 const: xlnx,zynqmp-firmware
26 - description: For implementations complying for Versal.
27 const: xlnx,versal-firmware
29 - description: For implementations complying for Versal NET.
32 - xlnx,versal-net-firmware
33 - const: xlnx,versal-firmware
37 The method of calling the PM-API firmware layer.
39 - "smc" : SMC #0, following the SMCCC
40 - "hvc" : HVC #0, following the SMCCC
42 $ref: /schemas/types.yaml#/definitions/string-array
47 "#power-domain-cells":
51 $ref: /schemas/clock/xlnx,versal-clk.yaml#
52 description: The clock controller is a hardware block of Xilinx versal
53 clock tree. It reads required input clock frequencies from the devicetree
54 and acts as clock provider for all clock consumers of PS clocks.list of
55 clock specifiers which are external input clocks to the given clock
60 $ref: /schemas/gpio/xlnx,zynqmp-gpio-modepin.yaml#
61 description: The gpio node describes connect to PS_MODE pins via firmware
66 $ref: /schemas/nvmem/xlnx,zynqmp-nvmem.yaml#
67 description: The ZynqMP MPSoC provides access to the hardware related data
68 like SOC revision, IDCODE and specific purpose efuses.
72 $ref: /schemas/fpga/xlnx,zynqmp-pcap-fpga.yaml
73 description: The ZynqMP SoC uses the PCAP (Processor Configuration Port) to
74 configure the Programmable Logic (PL). The configuration uses the
79 $ref: /schemas/pinctrl/xlnx,zynqmp-pinctrl.yaml#
80 description: The pinctrl node provides access to pinconfig and pincontrol
81 functionality available in firmware.
85 $ref: /schemas/power/reset/xlnx,zynqmp-power.yaml#
86 description: The zynqmp-power node describes the power management
87 configurations. It will control remote suspend/shutdown interfaces.
91 $ref: /schemas/reset/xlnx,zynqmp-reset.yaml#
92 description: The reset-controller node describes connection to the reset
93 functionality via firmware interface.
97 $ref: /schemas/fpga/xlnx,versal-fpga.yaml#
98 description: Compatible of the FPGA device.
102 $ref: /schemas/crypto/xlnx,zynqmp-aes.yaml#
103 description: The ZynqMP AES-GCM hardened cryptographic accelerator is
104 used to encrypt or decrypt the data with provided key and initialization
111 additionalProperties: false
115 #include <dt-bindings/power/xlnx-zynqmp-power.h>
117 zynqmp_firmware: zynqmp-firmware {
118 #power-domain-cells = <1>;
120 compatible = "xlnx,zynqmp-nvmem-fw";
122 compatible = "fixed-layout";
123 #address-cells = <1>;
126 soc_revision: soc-revision@0 {
132 compatible = "xlnx,zynqmp-gpio-modepin";
137 compatible = "xlnx,zynqmp-pcap-fpga";
140 compatible = "xlnx,zynqmp-pinctrl";
143 compatible = "xlnx,zynqmp-power";
144 interrupts = <0 35 4>;
147 compatible = "xlnx,zynqmp-reset";
154 power-domains = <&zynqmp_firmware PD_SATA>;
158 compatible = "xlnx,versal-firmware";
161 versal_fpga: versal-fpga {
162 compatible = "xlnx,versal-fpga";
165 xlnx_aes: zynqmp-aes {
166 compatible = "xlnx,zynqmp-aes";
169 versal_clk: clock-controller {
171 compatible = "xlnx,versal-clk";
172 clocks = <&ref>, <&pl_alt_ref>;
173 clock-names = "ref", "pl_alt_ref";