Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/dma/snps,dw-axi-dmac.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Synopsys DesignWare AXI DMA Controller
   8
   9 maintainers:
  10   - Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
  11   - Jee Heng Sia <jee.heng.sia@intel.com>
  12
  13 description:
  14   Synopsys DesignWare AXI DMA Controller DT Binding
  15
  16 allOf:
  17   - $ref: "dma-controller.yaml#"
  18
  19 properties:
  20   compatible:
  21     enum:
  22       - snps,axi-dma-1.01a
  23       - intel,kmb-axi-dma
  24
  25   reg:
  26     minItems: 1
  27     items:
  28       - description: Address range of the DMAC registers
  29       - description: Address range of the DMAC APB registers
  30
  31   reg-names:
  32     items:
  33       - const: axidma_ctrl_regs
  34       - const: axidma_apb_regs
  35
  36   interrupts:
  37     maxItems: 1
  38
  39   clocks:
  40     items:
  41       - description: Bus Clock
  42       - description: Module Clock
  43
  44   clock-names:
  45     items:
  46       - const: core-clk
  47       - const: cfgr-clk
  48
  49   '#dma-cells':
  50     const: 1
  51
  52   dma-channels:
  53     minimum: 1
  54     maximum: 8
  55
  56   snps,dma-masters:
  57     description: |
  58       Number of AXI masters supported by the hardware.
  59     $ref: /schemas/types.yaml#/definitions/uint32
  60     enum: [1, 2]
  61
  62   snps,data-width:
  63     description: |
  64       AXI data width supported by hardware.
  65       (0 - 8bits, 1 - 16bits, 2 - 32bits, ..., 6 - 512bits)
  66     $ref: /schemas/types.yaml#/definitions/uint32
  67     enum: [0, 1, 2, 3, 4, 5, 6]
  68
  69   snps,priority:
  70     description: |
  71       Channel priority specifier associated with the DMA channels.
  72     $ref: /schemas/types.yaml#/definitions/uint32-array
  73     minItems: 1
  74     maxItems: 8
  75
  76   snps,block-size:
  77     description: |
  78       Channel block size specifier associated with the DMA channels.
  79     $ref: /schemas/types.yaml#/definitions/uint32-array
  80     minItems: 1
  81     maxItems: 8
  82
  83   snps,axi-max-burst-len:
  84     description: |
  85       Restrict master AXI burst length by value specified in this property.
  86       If this property is missing the maximum AXI burst length supported by
  87       DMAC is used.
  88     $ref: /schemas/types.yaml#/definitions/uint32
  89     minimum: 1
  90     maximum: 256
  91
  92 required:
  93   - compatible
  94   - reg
  95   - clocks
  96   - clock-names
  97   - interrupts
  98   - '#dma-cells'
  99   - dma-channels
 100   - snps,dma-masters
 101   - snps,data-width
 102   - snps,priority
 103   - snps,block-size
 104
 105 additionalProperties: false
 106
 107 examples:
 108   - |
 109      #include <dt-bindings/interrupt-controller/arm-gic.h>
 110      #include <dt-bindings/interrupt-controller/irq.h>
 111      /* example with snps,dw-axi-dmac */
 112      dmac: dma-controller@80000 {
 113          compatible = "snps,axi-dma-1.01a";
 114          reg = <0x80000 0x400>;
 115          clocks = <&core_clk>, <&cfgr_clk>;
 116          clock-names = "core-clk", "cfgr-clk";
 117          interrupt-parent = <&intc>;
 118          interrupts = <27>;
 119          #dma-cells = <1>;
 120          dma-channels = <4>;
 121          snps,dma-masters = <2>;
 122          snps,data-width = <3>;
 123          snps,block-size = <4096 4096 4096 4096>;
 124          snps,priority = <0 1 2 3>;
 125          snps,axi-max-burst-len = <16>;
 126      };