1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/dma/renesas,rz-dmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas RZ/G2L DMA Controller
10 - Biju Das <biju.das.jz@bp.renesas.com>
13 - $ref: "dma-controller.yaml#"
19 - renesas,r9a07g044-dmac # RZ/G2{L,LC}
20 - const: renesas,rz-dmac
24 - description: Control and channel register block
25 - description: DMA extended resource selector block
52 - description: DMA main clock
53 - description: DMA register access clock
58 The cell specifies the encoded MID/RID values of the DMAC port
59 connected to the DMA client and the slave channel configuration
61 bits[0:9] - Specifies MID/RID value
62 bit[10] - Specifies DMA request high enable (HIEN)
63 bit[11] - Specifies DMA request detection type (LVL)
64 bits[12:14] - Specifies DMAACK output mode (AM)
65 bit[15] - Specifies Transfer Mode (TM)
75 - description: Reset for DMA ARESETN reset terminal
76 - description: Reset for DMA RST_ASYNC reset terminal
89 additionalProperties: false
93 #include <dt-bindings/interrupt-controller/arm-gic.h>
94 #include <dt-bindings/clock/r9a07g044-cpg.h>
96 dmac: dma-controller@11820000 {
97 compatible = "renesas,r9a07g044-dmac",
99 reg = <0x11820000 0x10000>,
100 <0x11830000 0x10000>;
101 interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>,
102 <GIC_SPI 125 IRQ_TYPE_EDGE_RISING>,
103 <GIC_SPI 126 IRQ_TYPE_EDGE_RISING>,
104 <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>,
105 <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>,
106 <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>,
107 <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>,
108 <GIC_SPI 131 IRQ_TYPE_EDGE_RISING>,
109 <GIC_SPI 132 IRQ_TYPE_EDGE_RISING>,
110 <GIC_SPI 133 IRQ_TYPE_EDGE_RISING>,
111 <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>,
112 <GIC_SPI 135 IRQ_TYPE_EDGE_RISING>,
113 <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>,
114 <GIC_SPI 137 IRQ_TYPE_EDGE_RISING>,
115 <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>,
116 <GIC_SPI 139 IRQ_TYPE_EDGE_RISING>,
117 <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>;
118 interrupt-names = "error",
119 "ch0", "ch1", "ch2", "ch3",
120 "ch4", "ch5", "ch6", "ch7",
121 "ch8", "ch9", "ch10", "ch11",
122 "ch12", "ch13", "ch14", "ch15";
123 clocks = <&cpg CPG_MOD R9A07G044_DMAC_ACLK>,
124 <&cpg CPG_MOD R9A07G044_DMAC_PCLK>;
125 power-domains = <&cpg>;
126 resets = <&cpg R9A07G044_DMAC_ARESETN>,
127 <&cpg R9A07G044_DMAC_RST_ASYNC>;