1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/dma/qcom,gpi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Technologies Inc GPI DMA controller
10 - Vinod Koul <vkoul@kernel.org>
13 QCOM GPI DMA controller provides DMA capabilities for
14 peripheral buses such as I2C, UART, and SPI.
17 - $ref: dma-controller.yaml#
27 - qcom,qdu1000-gpi-dma
34 - const: qcom,sm6350-gpi-dma
41 - const: qcom,sdm845-gpi-dma
48 Interrupt lines for each GPI instance
55 DMA clients must use the format described in dma.txt, giving a phandle
56 to the DMA controller plus the following 3 integer cells:
57 - channel: if set to 0xffffffff, any available channel will be allocated
58 for the client. Otherwise, the exact channel specified will be used.
59 - seid: serial id of the client as defined in the SoC documentation.
60 - client: type of the client as defined in dt-bindings/dma/qcom-gpi.h
80 additionalProperties: false
84 #include <dt-bindings/interrupt-controller/arm-gic.h>
85 #include <dt-bindings/dma/qcom-gpi.h>
86 gpi_dma0: dma-controller@800000 {
87 compatible = "qcom,sdm845-gpi-dma";
89 reg = <0x00800000 0x60000>;
90 iommus = <&apps_smmu 0x0016 0x0>;
92 dma-channel-mask = <0xfa>;
93 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
94 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
95 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
96 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
97 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
98 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
99 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
100 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
101 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
102 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
103 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
104 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
105 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;