1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/dma/fsl,edma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale enhanced Direct Memory Access(eDMA) Controller
10 The eDMA channels have multiplex capability by programmable
11 memory-mapped registers. channels are split into two groups, called
12 DMAMUX0 and DMAMUX1, specific DMA request source can only be multiplexed
13 by any channel of certain group, DMAMUX0 or DMAMUX1, but not both.
16 - Peng Fan <peng.fan@nxp.com>
25 - const: fsl,ls1028a-edma
26 - const: fsl,vf610-edma
54 If present registers and hardware scatter/gather descriptors of the
55 eDMA are implemented in big endian mode, otherwise in little mode.
67 - $ref: dma-controller.yaml#
92 const: fsl,imx7ulp-edma
104 unevaluatedProperties: false
108 #include <dt-bindings/interrupt-controller/arm-gic.h>
109 #include <dt-bindings/clock/vf610-clock.h>
111 edma0: dma-controller@40018000 {
113 compatible = "fsl,vf610-edma";
114 reg = <0x40018000 0x2000>,
117 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>,
118 <0 9 IRQ_TYPE_LEVEL_HIGH>;
119 interrupt-names = "edma-tx", "edma-err";
121 clock-names = "dmamux0", "dmamux1";
122 clocks = <&clks VF610_CLK_DMAMUX0>, <&clks VF610_CLK_DMAMUX1>;
126 #include <dt-bindings/interrupt-controller/arm-gic.h>
127 #include <dt-bindings/clock/imx7ulp-clock.h>
129 edma1: dma-controller@40080000 {
131 compatible = "fsl,imx7ulp-edma";
132 reg = <0x40080000 0x2000>,
135 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
136 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
137 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
138 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
139 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
140 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
141 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
142 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
143 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
144 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
145 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
146 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
147 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
148 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
149 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
150 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
151 /* last is eDMA2-ERR interrupt */
152 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
153 clock-names = "dma", "dmamux0";
154 clocks = <&pcc2 IMX7ULP_CLK_DMA1>, <&pcc2 IMX7ULP_CLK_DMA_MUX1>;