1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/dma/arm-pl08x.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM PrimeCells PL080 and PL081 and derivatives DMA controller
10 - Vinod Koul <vkoul@kernel.org>
13 - $ref: "dma-controller.yaml#"
15 # We need a select here so we don't match all nodes with 'arm,primecell'
33 - const: arm,primecell
35 - const: faraday,ftdma020
37 - const: arm,primecell
41 description: Address range of the PL08x registers
45 description: The PL08x interrupt number
49 description: The clock running the IP core clock
54 lli-bus-interface-ahb1:
56 description: if AHB master 1 is eligible for fetching LLIs
58 lli-bus-interface-ahb2:
60 description: if AHB master 2 is eligible for fetching LLIs
62 mem-bus-interface-ahb1:
64 description: if AHB master 1 is eligible for fetching memory contents
66 mem-bus-interface-ahb2:
68 description: if AHB master 2 is eligible for fetching memory contents
71 $ref: /schemas/types.yaml#/definitions/uint32
81 description: the size of the bursts for memcpy
84 $ref: /schemas/types.yaml#/definitions/uint32
90 description: bus width used for memcpy in bits. FTDMAC020 also accept 64 bits
99 unevaluatedProperties: false
103 dmac0: dma-controller@10130000 {
104 compatible = "arm,pl080", "arm,primecell";
105 reg = <0x10130000 0x1000>;
106 interrupt-parent = <&vica>;
108 clocks = <&hclkdma0>;
109 clock-names = "apb_pclk";
110 lli-bus-interface-ahb1;
111 lli-bus-interface-ahb2;
112 mem-bus-interface-ahb2;
113 memcpy-burst-size = <256>;
114 memcpy-bus-width = <32>;
118 #include <dt-bindings/interrupt-controller/irq.h>
119 #include <dt-bindings/reset/cortina,gemini-reset.h>
120 #include <dt-bindings/clock/cortina,gemini-clock.h>
121 dma-controller@67000000 {
122 compatible = "faraday,ftdma020", "arm,pl080", "arm,primecell";
123 /* Faraday Technology FTDMAC020 variant */
124 arm,primecell-periphid = <0x0003b080>;
125 reg = <0x67000000 0x1000>;
126 interrupts = <9 IRQ_TYPE_EDGE_RISING>;
127 resets = <&syscon GEMINI_RESET_DMAC>;
128 clocks = <&syscon GEMINI_CLK_AHB>;
129 clock-names = "apb_pclk";
130 /* Bus interface AHB1 (AHB0) is totally tilted */
131 lli-bus-interface-ahb2;
132 mem-bus-interface-ahb2;
133 memcpy-burst-size = <256>;
134 memcpy-bus-width = <32>;