1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/display/renesas,du.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car Display Unit (DU)
10 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
13 These DT bindings describe the Display Unit embedded in the Renesas R-Car
14 Gen1, R-Car Gen2, R-Car Gen3, RZ/G1 and RZ/G2 SoCs.
19 - renesas,du-r8a7742 # for RZ/G1H compatible DU
20 - renesas,du-r8a7743 # for RZ/G1M compatible DU
21 - renesas,du-r8a7744 # for RZ/G1N compatible DU
22 - renesas,du-r8a7745 # for RZ/G1E compatible DU
23 - renesas,du-r8a77470 # for RZ/G1C compatible DU
24 - renesas,du-r8a774a1 # for RZ/G2M compatible DU
25 - renesas,du-r8a774b1 # for RZ/G2N compatible DU
26 - renesas,du-r8a774c0 # for RZ/G2E compatible DU
27 - renesas,du-r8a774e1 # for RZ/G2H compatible DU
28 - renesas,du-r8a7779 # for R-Car H1 compatible DU
29 - renesas,du-r8a7790 # for R-Car H2 compatible DU
30 - renesas,du-r8a7791 # for R-Car M2-W compatible DU
31 - renesas,du-r8a7792 # for R-Car V2H compatible DU
32 - renesas,du-r8a7793 # for R-Car M2-N compatible DU
33 - renesas,du-r8a7794 # for R-Car E2 compatible DU
34 - renesas,du-r8a7795 # for R-Car H3 compatible DU
35 - renesas,du-r8a7796 # for R-Car M3-W compatible DU
36 - renesas,du-r8a77961 # for R-Car M3-W+ compatible DU
37 - renesas,du-r8a77965 # for R-Car M3-N compatible DU
38 - renesas,du-r8a77970 # for R-Car V3M compatible DU
39 - renesas,du-r8a77980 # for R-Car V3H compatible DU
40 - renesas,du-r8a77990 # for R-Car E3 compatible DU
41 - renesas,du-r8a77995 # for R-Car D3 compatible DU
46 # See compatible-specific constraints below.
50 description: Interrupt specifiers, one per DU channel
58 $ref: /schemas/graph.yaml#/properties/port
60 The connections to the DU output video ports are modeled using the OF
61 graph bindings specified in Documentation/devicetree/bindings/graph.txt.
62 The number of ports and their assignment are model-dependent. Each port
63 shall have a single endpoint.
67 $ref: /schemas/graph.yaml#/properties/port
68 unevaluatedProperties: false
74 unevaluatedProperties: false
77 $ref: "/schemas/types.yaml#/definitions/phandle-array"
79 A list of phandles to the CMM instances present in the SoC, one for each
83 $ref: "/schemas/types.yaml#/definitions/phandle-array"
85 A list of phandle and channel index tuples to the VSPs that handle the
86 memory interfaces for the DU channels. The phandle identifies the VSP
87 instance that serves the DU channel, and the channel index identifies
88 the LIF instance in that VSP.
103 const: renesas,du-r8a7779
110 - description: Functional clock
111 - description: DU_DOTCLKIN0 input clock
112 - description: DU_DOTCLKIN1 input clock
119 - pattern: '^dclkin\.[01]$'
120 - pattern: '^dclkin\.[01]$'
134 # port@2 is TCON, not supported yet
160 - description: Functional clock for DU0
161 - description: Functional clock for DU1
162 - description: DU_DOTCLKIN0 input clock
163 - description: DU_DOTCLKIN1 input clock
171 - pattern: '^dclkin\.[01]$'
172 - pattern: '^dclkin\.[01]$'
190 # port@2 is TCON, not supported yet
217 - description: Functional clock for DU0
218 - description: Functional clock for DU1
219 - description: DU_DOTCLKIN0 input clock
220 - description: DU_DOTCLKIN1 input clock
228 - pattern: '^dclkin\.[01]$'
229 - pattern: '^dclkin\.[01]$'
272 - description: Functional clock for DU0
273 - description: Functional clock for DU1
274 - description: DU_DOTCLKIN0 input clock
275 - description: DU_DOTCLKIN1 input clock
283 - pattern: '^dclkin\.[01]$'
284 - pattern: '^dclkin\.[01]$'
302 # port@2 is TCON, not supported yet
321 - renesas,du-r8a77470
328 - description: Functional clock for DU0
329 - description: Functional clock for DU1
330 - description: DU_DOTCLKIN0 input clock
331 - description: DU_DOTCLKIN1 input clock
339 - pattern: '^dclkin\.[01]$'
340 - pattern: '^dclkin\.[01]$'
360 # port@3 is DVENC, not supported yet
387 - description: Functional clock for DU0
388 - description: Functional clock for DU1
389 - description: Functional clock for DU2
390 - description: DU_DOTCLKIN0 input clock
391 - description: DU_DOTCLKIN1 input clock
392 - description: DU_DOTCLKIN2 input clock
401 - pattern: '^dclkin\.[012]$'
402 - pattern: '^dclkin\.[012]$'
403 - pattern: '^dclkin\.[012]$'
423 # port@3 is TCON, not supported yet
449 - description: Functional clock for DU0
450 - description: Functional clock for DU1
451 - description: Functional clock for DU2
452 - description: Functional clock for DU4
453 - description: DU_DOTCLKIN0 input clock
454 - description: DU_DOTCLKIN1 input clock
455 - description: DU_DOTCLKIN2 input clock
456 - description: DU_DOTCLKIN3 input clock
466 - pattern: '^dclkin\.[0123]$'
467 - pattern: '^dclkin\.[0123]$'
468 - pattern: '^dclkin\.[0123]$'
469 - pattern: '^dclkin\.[0123]$'
517 - renesas,du-r8a774a1
519 - renesas,du-r8a77961
526 - description: Functional clock for DU0
527 - description: Functional clock for DU1
528 - description: Functional clock for DU2
529 - description: DU_DOTCLKIN0 input clock
530 - description: DU_DOTCLKIN1 input clock
531 - description: DU_DOTCLKIN2 input clock
540 - pattern: '^dclkin\.[012]$'
541 - pattern: '^dclkin\.[012]$'
542 - pattern: '^dclkin\.[012]$'
588 - renesas,du-r8a774b1
589 - renesas,du-r8a774e1
590 - renesas,du-r8a77965
597 - description: Functional clock for DU0
598 - description: Functional clock for DU1
599 - description: Functional clock for DU3
600 - description: DU_DOTCLKIN0 input clock
601 - description: DU_DOTCLKIN1 input clock
602 - description: DU_DOTCLKIN3 input clock
611 - pattern: '^dclkin\.[013]$'
612 - pattern: '^dclkin\.[013]$'
613 - pattern: '^dclkin\.[013]$'
659 - renesas,du-r8a77970
660 - renesas,du-r8a77980
667 - description: Functional clock for DU0
668 - description: DU_DOTCLKIN0 input clock
715 - renesas,du-r8a774c0
716 - renesas,du-r8a77990
717 - renesas,du-r8a77995
724 - description: Functional clock for DU0
725 - description: Functional clock for DU1
726 - description: DU_DOTCLKIN0 input clock
727 - description: DU_DOTCLKIN1 input clock
735 - pattern: '^dclkin\.[01]$'
736 - pattern: '^dclkin\.[01]$'
756 # port@3 is TCON, not supported yet
777 additionalProperties: false
782 #include <dt-bindings/clock/renesas-cpg-mssr.h>
783 #include <dt-bindings/interrupt-controller/arm-gic.h>
786 compatible = "renesas,du-r8a7795";
787 reg = <0xfeb00000 0x80000>;
788 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
789 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
790 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
791 <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>;
792 clocks = <&cpg CPG_MOD 724>,
796 clock-names = "du.0", "du.1", "du.2", "du.3";
797 resets = <&cpg 724>, <&cpg 722>;
798 reset-names = "du.0", "du.2";
800 renesas,cmms = <&cmm0>, <&cmm1>, <&cmm2>, <&cmm3>;
801 renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>, <&vspd0 1>;
804 #address-cells = <1>;
810 remote-endpoint = <&adv7123_in>;
816 remote-endpoint = <&dw_hdmi0_in>;
822 remote-endpoint = <&dw_hdmi1_in>;
828 remote-endpoint = <&lvds0_in>;