1 # SPDX-License-Identifier: GPL-2.0-only
2 # Copyright 2019-2020, The Linux Foundation, All Rights Reserved
6 $id: http://devicetree.org/schemas/display/msm/gmu.yaml#
7 $schema: http://devicetree.org/meta-schemas/core.yaml#
9 title: GMU attached to certain Adreno GPUs
12 - Rob Clark <robdclark@gmail.com>
15 These bindings describe the Graphics Management Unit (GMU) that is attached
16 to members of the Adreno A6xx GPU family. The GMU provides on-device power
17 management and support to improve power efficiency and reduce the load on
24 - pattern: '^qcom,adreno-gmu-6[0-9][0-9]\.[0-9]$'
25 - const: qcom,adreno-gmu
26 - const: qcom,adreno-gmu-wrapper
46 - description: GMU HFI interrupt
47 - description: GMU interrupt
56 - description: CX power domain
57 - description: GX power domain
67 operating-points-v2: true
79 additionalProperties: false
87 - qcom,adreno-gmu-618.0
88 - qcom,adreno-gmu-630.2
93 - description: Core GMU registers
94 - description: GMU PDC registers
95 - description: GMU PDC sequence registers
103 - description: GMU clock
104 - description: GPU CX clock
105 - description: GPU AXI clock
106 - description: GPU MEMNOC clock
119 - qcom,adreno-gmu-635.0
120 - qcom,adreno-gmu-660.1
125 - description: Core GMU registers
126 - description: Resource controller registers
127 - description: GMU PDC registers
135 - description: GMU clock
136 - description: GPU CX clock
137 - description: GPU AXI clock
138 - description: GPU MEMNOC clock
139 - description: GPU AHB clock
140 - description: GPU HUB CX clock
141 - description: GPU SMMU vote clock
157 - qcom,adreno-gmu-640.1
162 - description: Core GMU registers
163 - description: GMU PDC registers
164 - description: GMU PDC sequence registers
176 - qcom,adreno-gmu-650.2
181 - description: Core GMU registers
182 - description: Resource controller registers
183 - description: GMU PDC registers
184 - description: GMU PDC sequence registers
197 - qcom,adreno-gmu-640.1
198 - qcom,adreno-gmu-650.2
203 - description: GPU AHB clock
204 - description: GMU clock
205 - description: GPU CX clock
206 - description: GPU AXI clock
207 - description: GPU MEMNOC clock
220 const: qcom,adreno-gmu-wrapper
225 - description: GMU wrapper register space
236 - operating-points-v2
240 #include <dt-bindings/clock/qcom,gpucc-sdm845.h>
241 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
242 #include <dt-bindings/interrupt-controller/irq.h>
243 #include <dt-bindings/interrupt-controller/arm-gic.h>
246 compatible = "qcom,adreno-gmu-630.2", "qcom,adreno-gmu";
248 reg = <0x506a000 0x30000>,
251 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
253 clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
254 <&gpucc GPU_CC_CXO_CLK>,
255 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
256 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
257 clock-names = "gmu", "cxo", "axi", "memnoc";
259 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
260 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
261 interrupt-names = "hfi", "gmu";
263 power-domains = <&gpucc GPU_CX_GDSC>,
264 <&gpucc GPU_GX_GDSC>;
265 power-domain-names = "cx", "gx";
267 iommus = <&adreno_smmu 5>;
268 operating-points-v2 = <&gmu_opp_table>;
271 gmu_wrapper: gmu@596a000 {
272 compatible = "qcom,adreno-gmu-wrapper";
273 reg = <0x0596a000 0x30000>;
275 power-domains = <&gpucc GPU_CX_GDSC>,
276 <&gpucc GPU_GX_GDSC>;
277 power-domain-names = "cx", "gx";