1 Qualcomm Technologies Inc. adreno/snapdragon DSI output
7 - reg: Physical base address and length of the registers of controller
8 - reg-names: The names of register regions. The following regions are required:
10 - interrupts: The interrupt signal from the DSI block.
11 - power-domains: Should be <&mmcc MDSS_GDSC>.
12 - clocks: Phandles to device clocks.
13 - clock-names: the following clocks are required:
21 For DSIv2, we need an additional clock:
23 For DSI6G v2.0 onwards, we need also need the clock:
25 - assigned-clocks: Parents of "byte" and "pixel" for the given platform.
26 - assigned-clock-parents: The Byte clock and Pixel clock PLL outputs provided
27 by a DSI PHY block. See [1] for details on clock bindings.
28 - vdd-supply: phandle to vdd regulator device node
29 - vddio-supply: phandle to vdd-io regulator device node
30 - vdda-supply: phandle to vdda regulator device node
31 - phys: phandle to DSI PHY device node
32 - phy-names: the name of the corresponding PHY device
33 - syscon-sfpb: A phandle to mmss_sfpb syscon node (only for DSIv2)
34 - ports: Contains 2 DSI controller ports as child nodes. Each port contains
35 an endpoint subnode as defined in [2] and [3].
38 - panel@0: Node of panel connected to this DSI controller.
39 See files in [4] for each supported panel.
40 - qcom,dual-dsi-mode: Boolean value indicating if the DSI controller is
41 driving a panel which needs 2 DSI links.
42 - qcom,master-dsi: Boolean value indicating if the DSI controller is driving
43 the master link of the 2-DSI panel.
44 - qcom,sync-dual-dsi: Boolean value indicating if the DSI controller is
45 driving a 2-DSI panel whose 2 links need receive command simultaneously.
46 - pinctrl-names: the pin control state names; should contain "default"
47 - pinctrl-0: the default pinctrl state (active)
48 - pinctrl-n: the "sleep" pinctrl state
49 - ports: contains DSI controller input and output ports as children, each
50 containing one endpoint subnode.
52 DSI Endpoint properties:
53 - remote-endpoint: For port@0, set to phandle of the connected panel/bridge's
54 input endpoint. For port@1, set to the MDP interface output. See [2] for
57 - data-lanes: this describes how the physical DSI data lanes are mapped
58 to the logical lanes on the given platform. The value contained in
59 index n describes what physical lane is mapped to the logical lane n
60 (DATAn, where n lies between 0 and 3). The clock lane position is fixed
61 and can't be changed. Hence, they aren't a part of the DT bindings. See
62 [3] for more info on the data-lanes property.
66 data-lanes = <3 0 1 2>;
68 The above mapping describes that the logical data lane DATA0 is mapped to
69 the physical data lane DATA3, logical DATA1 to physical DATA0, logic DATA2
70 to phys DATA1 and logic DATA3 to phys DATA2.
72 There are only a limited number of physical to logical mappings possible:
84 - compatible: Could be the following
85 * "qcom,dsi-phy-28nm-hpm"
86 * "qcom,dsi-phy-28nm-lp"
88 * "qcom,dsi-phy-28nm-8960"
91 - reg: Physical base address and length of the registers of PLL, PHY. Some
92 revisions require the PHY regulator base address, whereas others require the
93 PHY lane base address. See below for each PHY revision.
94 - reg-names: The names of register regions. The following regions are required:
95 For DSI 28nm HPM/LP/8960 PHYs and 20nm PHY:
99 For DSI 14nm and 10nm PHYs:
103 - clock-cells: Must be 1. The DSI PHY block acts as a clock provider, creating
104 2 clocks: A byte clock (index 0), and a pixel clock (index 1).
105 - power-domains: Should be <&mmcc MDSS_GDSC>.
106 - clocks: Phandles to device clocks. See [1] for details on clock bindings.
107 - clock-names: the following clocks are required:
109 * "ref" (only required for new DTS files/entries)
110 For 28nm HPM/LP, 28nm 8960 PHYs:
111 - vddio-supply: phandle to vdd-io regulator device node
113 - vddio-supply: phandle to vdd-io regulator device node
114 - vcca-supply: phandle to vcca regulator device node
116 - vcca-supply: phandle to vcca regulator device node
118 - vdds-supply: phandle to vdds regulator device node
121 - qcom,dsi-phy-regulator-ldo-mode: Boolean value indicating if the LDO mode PHY
123 - qcom,mdss-mdp-transfer-time-us: Specifies the dsi transfer time for command mode
124 panels in microseconds. Driver uses this number to adjust
125 the clock rate according to the expected transfer time.
126 Increasing this value would slow down the mdp processing
127 and can result in slower performance.
128 Decreasing this value can speed up the mdp processing,
129 but this can also impact power consumption.
130 As a rule this time should not be higher than the time
131 that would be expected with the processing at the
132 dsi link rate since anyways this would be the maximum
133 transfer time that could be achieved.
134 If ping pong split is enabled, this time should not be higher
135 than two times the dsi link rate time.
136 If the property is not specified, then the default value is 14000 us.
138 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
139 [2] Documentation/devicetree/bindings/graph.txt
140 [3] Documentation/devicetree/bindings/media/video-interfaces.txt
141 [4] Documentation/devicetree/bindings/display/panel/
145 compatible = "qcom,mdss-dsi-ctrl";
146 qcom,dsi-host-index = <0>;
147 interrupt-parent = <&mdp>;
149 reg-names = "dsi_ctrl";
150 reg = <0xfd922800 0x200>;
151 power-domains = <&mmcc MDSS_GDSC>;
161 <&mmcc MDSS_AXI_CLK>,
162 <&mmcc MDSS_BYTE0_CLK>,
163 <&mmcc MDSS_ESC0_CLK>,
164 <&mmcc MMSS_MISC_AHB_CLK>,
165 <&mmcc MDSS_AHB_CLK>,
166 <&mmcc MDSS_MDP_CLK>,
167 <&mmcc MDSS_PCLK0_CLK>;
170 <&mmcc BYTE0_CLK_SRC>,
171 <&mmcc PCLK0_CLK_SRC>;
172 assigned-clock-parents =
176 vdda-supply = <&pma8084_l2>;
177 vdd-supply = <&pma8084_l22>;
178 vddio-supply = <&pma8084_l12>;
181 phy-names ="dsi-phy";
187 qcom,mdss-mdp-transfer-time-us = <12000>;
189 pinctrl-names = "default", "sleep";
190 pinctrl-0 = <&dsi_active>;
191 pinctrl-1 = <&dsi_suspend>;
194 #address-cells = <1>;
200 remote-endpoint = <&mdp_intf1_out>;
207 remote-endpoint = <&panel_in>;
208 data-lanes = <0 1 2 3>;
214 compatible = "sharp,lq101r1sx01";
216 link2 = <&secondary>;
218 power-supply = <...>;
223 remote-endpoint = <&dsi0_out>;
229 dsi_phy0: dsi-phy@fd922a00 {
230 compatible = "qcom,dsi-phy-28nm-hpm";
231 qcom,dsi-phy-index = <0>;
236 reg = <0xfd922a00 0xd4>,
239 clock-names = "iface";
240 clocks = <&mmcc MDSS_AHB_CLK>;
242 vddio-supply = <&pma8084_l12>;
244 qcom,dsi-phy-regulator-ldo-mode;