1 # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
4 $id: http://devicetree.org/schemas/display/msm/dsi-controller-main.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Display DSI controller
10 - Krishna Manikandan <quic_mkrishn@quicinc.com>
13 - $ref: "../dsi-controller.yaml#"
19 - qcom,dsi-ctrl-6g-qcm2290
32 - description: Display byte clock
33 - description: Display byte interface clock
34 - description: Display pixel clock
35 - description: Display core clock
36 - description: Display AHB clock
37 - description: Display AXI clock
55 "#address-cells": true
60 description: A phandle to mmss_sfpb syscon node (only for DSIv2).
61 $ref: "/schemas/types.yaml#/definitions/phandle"
66 Indicates if the DSI controller is driving a panel which needs
72 Parents of "byte" and "pixel" for the given platform.
74 assigned-clock-parents:
77 The Byte clock and Pixel clock PLL outputs provided by a DSI PHY block.
82 operating-points-v2: true
88 $ref: "/schemas/graph.yaml#/properties/ports"
90 Contains DSI controller input and output ports as children, each
91 containing one endpoint subnode.
95 $ref: "/schemas/graph.yaml#/$defs/port-base"
96 unevaluatedProperties: false
98 Input endpoints of the controller.
101 $ref: /schemas/media/video-interfaces.yaml#
102 unevaluatedProperties: false
111 $ref: "/schemas/graph.yaml#/$defs/port-base"
112 unevaluatedProperties: false
114 Output endpoints of the controller.
117 $ref: /schemas/media/video-interfaces.yaml#
118 unevaluatedProperties: false
139 - assigned-clock-parents
142 additionalProperties: false
146 #include <dt-bindings/interrupt-controller/arm-gic.h>
147 #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
148 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
149 #include <dt-bindings/power/qcom-rpmpd.h>
152 compatible = "qcom,mdss-dsi-ctrl";
153 reg = <0x0ae94000 0x400>;
154 reg-names = "dsi_ctrl";
156 #address-cells = <1>;
159 interrupt-parent = <&mdss>;
162 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
163 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
164 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
165 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
166 <&dispcc DISP_CC_MDSS_AHB_CLK>,
167 <&dispcc DISP_CC_MDSS_AXI_CLK>;
168 clock-names = "byte",
178 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
179 assigned-clock-parents = <&dsi_phy 0>, <&dsi_phy 1>;
181 power-domains = <&rpmhpd SC7180_CX>;
182 operating-points-v2 = <&dsi_opp_table>;
185 #address-cells = <1>;
191 remote-endpoint = <&dpu_intf1_out>;
198 remote-endpoint = <&sn65dsi86_in>;
199 data-lanes = <0 1 2 3>;