Documentation/devicetree/bindings/display/msm/dpu-sc7280.yaml

   1 # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/display/msm/dpu-sc7280.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Qualcomm Display DPU dt properties for SC7280
   8
   9 maintainers:
  10   - Krishna Manikandan <quic_mkrishn@quicinc.com>
  11
  12 description: |
  13   Device tree bindings for MSM Mobile Display Subsystem (MDSS) that encapsulates
  14   sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
  15   bindings of MDSS and DPU are mentioned for SC7280.
  16
  17 $ref: /schemas/display/msm/mdss-common.yaml#
  18
  19 properties:
  20   compatible:
  21     const: qcom,sc7280-mdss
  22
  23   clocks:
  24     items:
  25       - description: Display AHB clock from gcc
  26       - description: Display AHB clock from dispcc
  27       - description: Display core clock
  28
  29   clock-names:
  30     items:
  31       - const: iface
  32       - const: ahb
  33       - const: core
  34
  35   iommus:
  36     maxItems: 1
  37
  38   interconnects:
  39     maxItems: 1
  40
  41   interconnect-names:
  42     maxItems: 1
  43
  44 patternProperties:
  45   "^display-controller@[0-9a-f]+$":
  46     type: object
  47     $ref: /schemas/display/msm/dpu-common.yaml#
  48     description: Node containing the properties of DPU.
  49     unevaluatedProperties: false
  50
  51     properties:
  52       compatible:
  53         const: qcom,sc7280-dpu
  54
  55       reg:
  56         items:
  57           - description: Address offset and size for mdp register set
  58           - description: Address offset and size for vbif register set
  59
  60       reg-names:
  61         items:
  62           - const: mdp
  63           - const: vbif
  64
  65       clocks:
  66         items:
  67           - description: Display hf axi clock
  68           - description: Display sf axi clock
  69           - description: Display ahb clock
  70           - description: Display lut clock
  71           - description: Display core clock
  72           - description: Display vsync clock
  73
  74       clock-names:
  75         items:
  76           - const: bus
  77           - const: nrt_bus
  78           - const: iface
  79           - const: lut
  80           - const: core
  81           - const: vsync
  82
  83 unevaluatedProperties: false
  84
  85 examples:
  86   - |
  87     #include <dt-bindings/clock/qcom,dispcc-sc7280.h>
  88     #include <dt-bindings/clock/qcom,gcc-sc7280.h>
  89     #include <dt-bindings/interrupt-controller/arm-gic.h>
  90     #include <dt-bindings/interconnect/qcom,sc7280.h>
  91     #include <dt-bindings/power/qcom-rpmpd.h>
  92
  93     display-subsystem@ae00000 {
  94          #address-cells = <1>;
  95          #size-cells = <1>;
  96          compatible = "qcom,sc7280-mdss";
  97          reg = <0xae00000 0x1000>;
  98          reg-names = "mdss";
  99          power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>;
 100          clocks = <&gcc GCC_DISP_AHB_CLK>,
 101                   <&dispcc DISP_CC_MDSS_AHB_CLK>,
 102                   <&dispcc DISP_CC_MDSS_MDP_CLK>;
 103          clock-names = "iface",
 104                        "ahb",
 105                        "core";
 106
 107          interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 108          interrupt-controller;
 109          #interrupt-cells = <1>;
 110
 111          interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>;
 112          interconnect-names = "mdp0-mem";
 113
 114          iommus = <&apps_smmu 0x900 0x402>;
 115          ranges;
 116
 117          display-controller@ae01000 {
 118                    compatible = "qcom,sc7280-dpu";
 119                    reg = <0x0ae01000 0x8f000>,
 120                          <0x0aeb0000 0x2008>;
 121
 122                    reg-names = "mdp", "vbif";
 123
 124                    clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
 125                             <&gcc GCC_DISP_SF_AXI_CLK>,
 126                             <&dispcc DISP_CC_MDSS_AHB_CLK>,
 127                             <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
 128                             <&dispcc DISP_CC_MDSS_MDP_CLK>,
 129                             <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
 130                    clock-names = "bus",
 131                                  "nrt_bus",
 132                                  "iface",
 133                                  "lut",
 134                                  "core",
 135                                  "vsync";
 136
 137                    interrupt-parent = <&mdss>;
 138                    interrupts = <0>;
 139                    power-domains = <&rpmhpd SC7280_CX>;
 140                    operating-points-v2 = <&mdp_opp_table>;
 141
 142                    ports {
 143                            #address-cells = <1>;
 144                            #size-cells = <0>;
 145
 146                            port@0 {
 147                                    reg = <0>;
 148                                    dpu_intf1_out: endpoint {
 149                                            remote-endpoint = <&dsi0_in>;
 150                                    };
 151                            };
 152
 153                            port@1 {
 154                                    reg = <1>;
 155                                    dpu_intf5_out: endpoint {
 156                                            remote-endpoint = <&edp_in>;
 157                                    };
 158                            };
 159                    };
 160          };
 161     };
 162 ...