1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/display/mediatek/mediatek,ovl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Mediatek display overlay
10 - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11 - Philipp Zabel <p.zabel@pengutronix.de>
14 Mediatek display overlay, namely OVL, can do alpha blending from
16 OVL device node must be siblings to the central MMSYS_CONFIG node.
17 For a description of the MMSYS_CONFIG binding, see
18 Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
25 - const: mediatek,mt2701-disp-ovl
27 - const: mediatek,mt8173-disp-ovl
29 - const: mediatek,mt8183-disp-ovl
31 - const: mediatek,mt8192-disp-ovl
34 - mediatek,mt7623-disp-ovl
35 - mediatek,mt2712-disp-ovl
37 - mediatek,mt2701-disp-ovl
40 - mediatek,mt8195-disp-ovl
42 - mediatek,mt8183-disp-ovl
51 description: A phandle and PM domain specifier as defined by bindings of
52 the power controller specified by phandle. See
53 Documentation/devicetree/bindings/power/power-domain.yaml for details.
57 - description: OVL Clock
61 This property should point to the respective IOMMU block with master port as argument,
62 see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
64 mediatek,gce-client-reg:
65 description: The register of client driver can be configured by gce with
66 4 arguments defined in this property, such as phandle of gce, subsys id,
67 register offset and size. Each GCE subsys id is mapping to a client
68 defined in the header include/dt-bindings/gce/<chip>-gce.h.
69 $ref: /schemas/types.yaml#/definitions/phandle-array
80 additionalProperties: false
86 compatible = "mediatek,mt8173-disp-ovl";
87 reg = <0 0x1400c000 0 0x1000>;
88 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>;
89 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
90 clocks = <&mmsys CLK_MM_DISP_OVL0>;
91 iommus = <&iommu M4U_PORT_DISP_OVL0>;
92 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;