Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/display/mediatek/mediatek,color.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Mediatek display color processor
   8
   9 maintainers:
  10   - Chun-Kuang Hu <chunkuang.hu@kernel.org>
  11   - Philipp Zabel <p.zabel@pengutronix.de>
  12
  13 description: |
  14   Mediatek display color processor, namely COLOR, provides hue, luma and
  15   saturation adjustments to get better picture quality and to have one panel
  16   resemble the other in their output characteristics.
  17   COLOR device node must be siblings to the central MMSYS_CONFIG node.
  18   For a description of the MMSYS_CONFIG binding, see
  19   Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
  20   for details.
  21
  22 properties:
  23   compatible:
  24     oneOf:
  25       - items:
  26           - const: mediatek,mt2701-disp-color
  27       - items:
  28           - const: mediatek,mt8167-disp-color
  29       - items:
  30           - const: mediatek,mt8173-disp-color
  31       - items:
  32           - enum:
  33               - mediatek,mt7623-disp-color
  34               - mediatek,mt2712-disp-color
  35           - enum:
  36               - mediatek,mt2701-disp-color
  37       - items:
  38           - enum:
  39               - mediatek,mt8183-disp-color
  40               - mediatek,mt8192-disp-color
  41               - mediatek,mt8195-disp-color
  42           - enum:
  43               - mediatek,mt8173-disp-color
  44   reg:
  45     maxItems: 1
  46
  47   interrupts:
  48     maxItems: 1
  49
  50   power-domains:
  51     description: A phandle and PM domain specifier as defined by bindings of
  52       the power controller specified by phandle. See
  53       Documentation/devicetree/bindings/power/power-domain.yaml for details.
  54
  55   clocks:
  56     items:
  57       - description: COLOR Clock
  58
  59   mediatek,gce-client-reg:
  60     description: The register of client driver can be configured by gce with
  61       4 arguments defined in this property, such as phandle of gce, subsys id,
  62       register offset and size. Each GCE subsys id is mapping to a client
  63       defined in the header include/dt-bindings/gce/<chip>-gce.h.
  64     $ref: /schemas/types.yaml#/definitions/phandle-array
  65     maxItems: 1
  66
  67 required:
  68   - compatible
  69   - reg
  70   - interrupts
  71   - power-domains
  72   - clocks
  73
  74 additionalProperties: false
  75
  76 examples:
  77   - |
  78     #include <dt-bindings/interrupt-controller/arm-gic.h>
  79     #include <dt-bindings/clock/mt8173-clk.h>
  80     #include <dt-bindings/power/mt8173-power.h>
  81     #include <dt-bindings/gce/mt8173-gce.h>
  82
  83     soc {
  84         #address-cells = <2>;
  85         #size-cells = <2>;
  86
  87         color0: color@14013000 {
  88             compatible = "mediatek,mt8173-disp-color";
  89             reg = <0 0x14013000 0 0x1000>;
  90             interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>;
  91             power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
  92             clocks = <&mmsys CLK_MM_DISP_COLOR0>;
  93             mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x3000 0x1000>;
  94         };
  95     };