Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/display/bridge/ti,sn65dsi86.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: SN65DSI86 DSI to eDP bridge chip
   8
   9 maintainers:
  10   - Sandeep Panda <spanda@codeaurora.org>
  11
  12 description: |
  13   The Texas Instruments SN65DSI86 bridge takes MIPI DSI in and outputs eDP.
  14   https://www.ti.com/general/docs/lit/getliterature.tsp?genericPartNumber=sn65dsi86&fileType=pdf
  15
  16 properties:
  17   compatible:
  18     const: ti,sn65dsi86
  19
  20   reg:
  21     const: 0x2d
  22
  23   enable-gpios:
  24     maxItems: 1
  25     description: GPIO specifier for bridge_en pin (active high).
  26
  27   suspend-gpios:
  28     maxItems: 1
  29     description: GPIO specifier for GPIO1 pin on bridge (active low).
  30
  31   no-hpd:
  32     type: boolean
  33     description:
  34       Set if the HPD line on the bridge isn't hooked up to anything or is
  35       otherwise unusable.
  36
  37   vccio-supply:
  38     description: A 1.8V supply that powers the digital IOs.
  39
  40   vpll-supply:
  41     description: A 1.8V supply that powers the DisplayPort PLL.
  42
  43   vcca-supply:
  44     description: A 1.2V supply that powers the analog circuits.
  45
  46   vcc-supply:
  47     description: A 1.2V supply that powers the digital core.
  48
  49   interrupts:
  50     maxItems: 1
  51
  52   clocks:
  53     maxItems: 1
  54     description:
  55       Clock specifier for input reference clock. The reference clock rate must
  56       be 12 MHz, 19.2 MHz, 26 MHz, 27 MHz or 38.4 MHz.
  57
  58   clock-names:
  59     const: refclk
  60
  61   gpio-controller: true
  62   '#gpio-cells':
  63     const: 2
  64     description:
  65       First cell is pin number, second cell is flags.  GPIO pin numbers are
  66       1-based to match the datasheet.  See ../../gpio/gpio.txt for more
  67       information.
  68
  69   '#pwm-cells':
  70     const: 1
  71     description: See ../../pwm/pwm.yaml for description of the cell formats.
  72
  73   aux-bus:
  74     $ref: /schemas/display/dp-aux-bus.yaml#
  75
  76   ports:
  77     $ref: /schemas/graph.yaml#/properties/ports
  78
  79     properties:
  80       port@0:
  81         $ref: /schemas/graph.yaml#/properties/port
  82         description:
  83           Video port for MIPI DSI input
  84
  85       port@1:
  86         $ref: /schemas/graph.yaml#/$defs/port-base
  87         unevaluatedProperties: false
  88         description:
  89           Video port for eDP output (panel or connector).
  90
  91         properties:
  92           endpoint:
  93             $ref: /schemas/graph.yaml#/$defs/endpoint-base
  94             unevaluatedProperties: false
  95
  96             properties:
  97               data-lanes:
  98                 oneOf:
  99                   - minItems: 1
 100                     maxItems: 1
 101                     uniqueItems: true
 102                     items:
 103                       enum:
 104                         - 0
 105                         - 1
 106                     description:
 107                       If you have 1 logical lane the bridge supports routing
 108                       to either port 0 or port 1.  Port 0 is suggested.
 109                       See ../../media/video-interface.txt for details.
 110
 111                   - minItems: 2
 112                     maxItems: 2
 113                     uniqueItems: true
 114                     items:
 115                       enum:
 116                         - 0
 117                         - 1
 118                     description:
 119                       If you have 2 logical lanes the bridge supports
 120                       reordering but only on physical ports 0 and 1.
 121                       See ../../media/video-interface.txt for details.
 122
 123                   - minItems: 4
 124                     maxItems: 4
 125                     uniqueItems: true
 126                     items:
 127                       enum:
 128                         - 0
 129                         - 1
 130                         - 2
 131                         - 3
 132                     description:
 133                       If you have 4 logical lanes the bridge supports
 134                       reordering in any way.
 135                       See ../../media/video-interface.txt for details.
 136
 137               lane-polarities:
 138                 minItems: 1
 139                 maxItems: 4
 140                 items:
 141                   enum:
 142                     - 0
 143                     - 1
 144                 description: See ../../media/video-interface.txt
 145
 146             dependencies:
 147               lane-polarities: [data-lanes]
 148
 149     required:
 150       - port@0
 151       - port@1
 152
 153 required:
 154   - compatible
 155   - reg
 156   - enable-gpios
 157   - vccio-supply
 158   - vpll-supply
 159   - vcca-supply
 160   - vcc-supply
 161   - ports
 162
 163 additionalProperties: false
 164
 165 examples:
 166   - |
 167     #include <dt-bindings/clock/qcom,rpmh.h>
 168     #include <dt-bindings/gpio/gpio.h>
 169     #include <dt-bindings/interrupt-controller/irq.h>
 170
 171     i2c {
 172       #address-cells = <1>;
 173       #size-cells = <0>;
 174
 175       bridge@2d {
 176         compatible = "ti,sn65dsi86";
 177         reg = <0x2d>;
 178
 179         interrupt-parent = <&tlmm>;
 180         interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
 181
 182         enable-gpios = <&tlmm 102 GPIO_ACTIVE_HIGH>;
 183
 184         vpll-supply = <&src_pp1800_s4a>;
 185         vccio-supply = <&src_pp1800_s4a>;
 186         vcca-supply = <&src_pp1200_l2a>;
 187         vcc-supply = <&src_pp1200_l2a>;
 188
 189         clocks = <&rpmhcc RPMH_LN_BB_CLK2>;
 190         clock-names = "refclk";
 191
 192         no-hpd;
 193
 194         ports {
 195           #address-cells = <1>;
 196           #size-cells = <0>;
 197
 198           port@0 {
 199             reg = <0>;
 200             endpoint {
 201               remote-endpoint = <&dsi0_out>;
 202             };
 203           };
 204
 205           port@1 {
 206             reg = <1>;
 207             sn65dsi86_out: endpoint {
 208               remote-endpoint = <&panel_in_edp>;
 209             };
 210           };
 211         };
 212
 213         aux-bus {
 214           panel {
 215             compatible = "boe,nv133fhm-n62";
 216             power-supply = <&pp3300_dx_edp>;
 217             backlight = <&backlight>;
 218             hpd-gpios = <&sn65dsi86_bridge 2 GPIO_ACTIVE_HIGH>;
 219
 220             port {
 221               panel_in_edp: endpoint {
 222                 remote-endpoint = <&sn65dsi86_out>;
 223               };
 224             };
 225           };
 226         };
 227       };
 228     };
 229   - |
 230     #include <dt-bindings/clock/qcom,rpmh.h>
 231     #include <dt-bindings/gpio/gpio.h>
 232     #include <dt-bindings/interrupt-controller/irq.h>
 233
 234     i2c {
 235       #address-cells = <1>;
 236       #size-cells = <0>;
 237
 238       bridge@2d {
 239         compatible = "ti,sn65dsi86";
 240         reg = <0x2d>;
 241
 242         enable-gpios = <&msmgpio 33 GPIO_ACTIVE_HIGH>;
 243         suspend-gpios = <&msmgpio 34 GPIO_ACTIVE_LOW>;
 244
 245         interrupts-extended = <&gpio3 4 IRQ_TYPE_EDGE_FALLING>;
 246
 247         vccio-supply = <&pm8916_l17>;
 248         vcca-supply = <&pm8916_l6>;
 249         vpll-supply = <&pm8916_l17>;
 250         vcc-supply = <&pm8916_l6>;
 251
 252         clock-names = "refclk";
 253         clocks = <&input_refclk>;
 254
 255         ports {
 256           #address-cells = <1>;
 257           #size-cells = <0>;
 258
 259           port@0 {
 260             reg = <0>;
 261
 262             edp_bridge_in: endpoint {
 263               remote-endpoint = <&dsi_out>;
 264             };
 265           };
 266
 267           port@1 {
 268             reg = <1>;
 269
 270             edp_bridge_out: endpoint {
 271               data-lanes = <2 1 3 0>;
 272               lane-polarities = <0 1 0 1>;
 273               remote-endpoint = <&edp_panel_in>;
 274             };
 275           };
 276         };
 277       };
 278     };