1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/display/bridge/renesas,dsi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas RZ/G2L MIPI DSI Encoder
10 - Biju Das <biju.das.jz@bp.renesas.com>
13 This binding describes the MIPI DSI encoder embedded in the Renesas
14 RZ/G2L alike family of SoC's. The encoder can operate in DSI mode, with
15 up to four data lanes.
18 - $ref: /schemas/display/dsi-controller.yaml#
24 - renesas,r9a07g044-mipi-dsi # RZ/G2{L,LC}
25 - renesas,r9a07g054-mipi-dsi # RZ/V2L
26 - const: renesas,rzg2l-mipi-dsi
33 - description: Sequence operation channel 0 interrupt
34 - description: Sequence operation channel 1 interrupt
35 - description: Video-Input operation channel 1 interrupt
36 - description: DSI Packet Receive interrupt
37 - description: DSI Fatal Error interrupt
38 - description: DSI D-PHY PPI interrupt
39 - description: Debug interrupt
53 - description: DSI D-PHY PLL multiplied clock
54 - description: DSI D-PHY system clock
55 - description: DSI AXI bus clock
56 - description: DSI Register access clock
57 - description: DSI Video clock
58 - description: DSI D-PHY Escape mode transmit clock
71 - description: MIPI_DSI_CMN_RSTB
72 - description: MIPI_DSI_ARESET_N
73 - description: MIPI_DSI_PRESET_N
85 $ref: /schemas/graph.yaml#/properties/ports
89 $ref: /schemas/graph.yaml#/properties/port
90 description: Parallel input port
93 $ref: /schemas/graph.yaml#/$defs/port-base
94 unevaluatedProperties: false
95 description: DSI output port
99 $ref: /schemas/media/video-interfaces.yaml#
100 unevaluatedProperties: false
104 description: array of physical DSI data lane indexes.
131 additionalProperties: false
135 #include <dt-bindings/clock/r9a07g044-cpg.h>
136 #include <dt-bindings/interrupt-controller/arm-gic.h>
139 compatible = "renesas,r9a07g044-mipi-dsi", "renesas,rzg2l-mipi-dsi";
140 reg = <0x10850000 0x20000>;
141 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
142 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
143 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
144 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
145 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
146 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
147 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
148 interrupt-names = "seq0", "seq1", "vin1", "rcv",
149 "ferr", "ppi", "debug";
150 clocks = <&cpg CPG_MOD R9A07G044_MIPI_DSI_PLLCLK>,
151 <&cpg CPG_MOD R9A07G044_MIPI_DSI_SYSCLK>,
152 <&cpg CPG_MOD R9A07G044_MIPI_DSI_ACLK>,
153 <&cpg CPG_MOD R9A07G044_MIPI_DSI_PCLK>,
154 <&cpg CPG_MOD R9A07G044_MIPI_DSI_VCLK>,
155 <&cpg CPG_MOD R9A07G044_MIPI_DSI_LPCLK>;
156 clock-names = "pllclk", "sysclk", "aclk", "pclk", "vclk", "lpclk";
157 resets = <&cpg R9A07G044_MIPI_DSI_CMN_RSTB>,
158 <&cpg R9A07G044_MIPI_DSI_ARESET_N>,
159 <&cpg R9A07G044_MIPI_DSI_PRESET_N>;
160 reset-names = "rst", "arst", "prst";
161 power-domains = <&cpg>;
164 #address-cells = <1>;
170 remote-endpoint = <&du_out_dsi0>;
177 data-lanes = <1 2 3 4>;
178 remote-endpoint = <&adv7535_in>;