Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/display/bridge/nwl-dsi.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Northwest Logic MIPI-DSI controller on i.MX SoCs
   8
   9 maintainers:
  10   - Guido Gúnther <agx@sigxcpu.org>
  11   - Robert Chiras <robert.chiras@nxp.com>
  12
  13 description: |
  14   NWL MIPI-DSI host controller found on i.MX8 platforms. This is a dsi bridge for
  15   the SOCs NWL MIPI-DSI host controller.
  16
  17 properties:
  18   compatible:
  19     const: fsl,imx8mq-nwl-dsi
  20
  21   reg:
  22     maxItems: 1
  23
  24   interrupts:
  25     maxItems: 1
  26
  27   '#address-cells':
  28     const: 1
  29
  30   '#size-cells':
  31     const: 0
  32
  33   clocks:
  34     items:
  35       - description: DSI core clock
  36       - description: RX_ESC clock (used in escape mode)
  37       - description: TX_ESC clock (used in escape mode)
  38       - description: PHY_REF clock
  39       - description: LCDIF clock
  40
  41   clock-names:
  42     items:
  43       - const: core
  44       - const: rx_esc
  45       - const: tx_esc
  46       - const: phy_ref
  47       - const: lcdif
  48
  49   mux-controls:
  50     description:
  51       mux controller node to use for operating the input mux
  52
  53   phys:
  54     maxItems: 1
  55     description:
  56       A phandle to the phy module representing the DPHY
  57
  58   phy-names:
  59     items:
  60       - const: dphy
  61
  62   power-domains:
  63     maxItems: 1
  64
  65   resets:
  66     items:
  67       - description: dsi byte reset line
  68       - description: dsi dpi reset line
  69       - description: dsi esc reset line
  70       - description: dsi pclk reset line
  71
  72   reset-names:
  73     items:
  74       - const: byte
  75       - const: dpi
  76       - const: esc
  77       - const: pclk
  78
  79   ports:
  80     type: object
  81     description:
  82       A node containing DSI input & output port nodes with endpoint
  83       definitions as documented in
  84       Documentation/devicetree/bindings/graph.txt.
  85     properties:
  86       port@0:
  87         type: object
  88         description:
  89           Input port node to receive pixel data from the
  90           display controller. Exactly one endpoint must be
  91           specified.
  92         properties:
  93           '#address-cells':
  94             const: 1
  95
  96           '#size-cells':
  97             const: 0
  98
  99           endpoint@0:
 100             description: sub-node describing the input from LCDIF
 101             type: object
 102
 103           endpoint@1:
 104             description: sub-node describing the input from DCSS
 105             type: object
 106
 107           reg:
 108             const: 0
 109
 110         required:
 111           - '#address-cells'
 112           - '#size-cells'
 113           - reg
 114
 115         oneOf:
 116           - required:
 117               - endpoint@0
 118           - required:
 119               - endpoint@1
 120
 121         additionalProperties: false
 122
 123       port@1:
 124         type: object
 125         description:
 126           DSI output port node to the panel or the next bridge
 127           in the chain
 128
 129       '#address-cells':
 130         const: 1
 131
 132       '#size-cells':
 133         const: 0
 134
 135     required:
 136       - '#address-cells'
 137       - '#size-cells'
 138       - port@0
 139       - port@1
 140
 141     additionalProperties: false
 142
 143 patternProperties:
 144   "^panel@[0-9]+$":
 145     type: object
 146
 147 required:
 148   - '#address-cells'
 149   - '#size-cells'
 150   - clock-names
 151   - clocks
 152   - compatible
 153   - interrupts
 154   - mux-controls
 155   - phy-names
 156   - phys
 157   - ports
 158   - reg
 159   - reset-names
 160   - resets
 161
 162 additionalProperties: false
 163
 164 examples:
 165  - |
 166
 167    #include <dt-bindings/clock/imx8mq-clock.h>
 168    #include <dt-bindings/gpio/gpio.h>
 169    #include <dt-bindings/interrupt-controller/arm-gic.h>
 170    #include <dt-bindings/reset/imx8mq-reset.h>
 171
 172    mipi_dsi: mipi_dsi@30a00000 {
 173               #address-cells = <1>;
 174               #size-cells = <0>;
 175               compatible = "fsl,imx8mq-nwl-dsi";
 176               reg = <0x30A00000 0x300>;
 177               clocks = <&clk IMX8MQ_CLK_DSI_CORE>,
 178                        <&clk IMX8MQ_CLK_DSI_AHB>,
 179                        <&clk IMX8MQ_CLK_DSI_IPG_DIV>,
 180                        <&clk IMX8MQ_CLK_DSI_PHY_REF>,
 181                        <&clk IMX8MQ_CLK_LCDIF_PIXEL>;
 182               clock-names = "core", "rx_esc", "tx_esc", "phy_ref", "lcdif";
 183               interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 184               mux-controls = <&mux 0>;
 185               power-domains = <&pgc_mipi>;
 186               resets = <&src IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N>,
 187                        <&src IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N>,
 188                        <&src IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N>,
 189                        <&src IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N>;
 190               reset-names = "byte", "dpi", "esc", "pclk";
 191               phys = <&dphy>;
 192               phy-names = "dphy";
 193
 194               panel@0 {
 195                       compatible = "rocktech,jh057n00900";
 196                       reg = <0>;
 197                       vcc-supply = <&reg_2v8_p>;
 198                       iovcc-supply = <&reg_1v8_p>;
 199                       reset-gpios = <&gpio3 13 GPIO_ACTIVE_LOW>;
 200                       port {
 201                            panel_in: endpoint {
 202                                      remote-endpoint = <&mipi_dsi_out>;
 203                            };
 204                       };
 205               };
 206
 207               ports {
 208                     #address-cells = <1>;
 209                     #size-cells = <0>;
 210
 211                     port@0 {
 212                            #size-cells = <0>;
 213                            #address-cells = <1>;
 214                            reg = <0>;
 215                            mipi_dsi_in: endpoint@0 {
 216                                         reg = <0>;
 217                                         remote-endpoint = <&lcdif_mipi_dsi>;
 218                            };
 219                     };
 220                     port@1 {
 221                            reg = <1>;
 222                            mipi_dsi_out: endpoint {
 223                                          remote-endpoint = <&panel_in>;
 224                            };
 225                     };
 226               };
 227       };