1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/display/bridge/nwl-dsi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Northwest Logic MIPI-DSI controller on i.MX SoCs
10 - Guido GĂșnther <agx@sigxcpu.org>
11 - Robert Chiras <robert.chiras@nxp.com>
14 NWL MIPI-DSI host controller found on i.MX8 platforms. This is a dsi bridge for
15 the SOCs NWL MIPI-DSI host controller.
19 const: fsl,imx8mq-nwl-dsi
35 - description: DSI core clock
36 - description: RX_ESC clock (used in escape mode)
37 - description: TX_ESC clock (used in escape mode)
38 - description: PHY_REF clock
39 - description: LCDIF clock
51 mux controller node to use for operating the input mux
56 A phandle to the phy module representing the DPHY
67 - description: dsi byte reset line
68 - description: dsi dpi reset line
69 - description: dsi esc reset line
70 - description: dsi pclk reset line
82 A node containing DSI input & output port nodes with endpoint
83 definitions as documented in
84 Documentation/devicetree/bindings/graph.txt.
89 Input port node to receive pixel data from the
90 display controller. Exactly one endpoint must be
100 description: sub-node describing the input from LCDIF
104 description: sub-node describing the input from DCSS
121 additionalProperties: false
126 DSI output port node to the panel or the next bridge
141 additionalProperties: false
162 additionalProperties: false
167 #include <dt-bindings/clock/imx8mq-clock.h>
168 #include <dt-bindings/interrupt-controller/arm-gic.h>
169 #include <dt-bindings/reset/imx8mq-reset.h>
171 mipi_dsi: mipi_dsi@30a00000 {
172 #address-cells = <1>;
174 compatible = "fsl,imx8mq-nwl-dsi";
175 reg = <0x30A00000 0x300>;
176 clocks = <&clk IMX8MQ_CLK_DSI_CORE>,
177 <&clk IMX8MQ_CLK_DSI_AHB>,
178 <&clk IMX8MQ_CLK_DSI_IPG_DIV>,
179 <&clk IMX8MQ_CLK_DSI_PHY_REF>,
180 <&clk IMX8MQ_CLK_LCDIF_PIXEL>;
181 clock-names = "core", "rx_esc", "tx_esc", "phy_ref", "lcdif";
182 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
183 mux-controls = <&mux 0>;
184 power-domains = <&pgc_mipi>;
185 resets = <&src IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N>,
186 <&src IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N>,
187 <&src IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N>,
188 <&src IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N>;
189 reset-names = "byte", "dpi", "esc", "pclk";
194 #address-cells = <1>;
196 compatible = "rocktech,jh057n00900";
201 remote-endpoint = <&mipi_dsi_out>;
207 #address-cells = <1>;
212 #address-cells = <1>;
214 mipi_dsi_in: endpoint@0 {
216 remote-endpoint = <&lcdif_mipi_dsi>;
221 mipi_dsi_out: endpoint {
222 remote-endpoint = <&panel_in>;