1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/display/bridge/fsl,imx93-mipi-dsi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX93 specific extensions to Synopsys Designware MIPI DSI
10 - Liu Ying <victor.liu@nxp.com>
13 There is a Synopsys Designware MIPI DSI Host Controller and a Synopsys
14 Designware MIPI DPHY embedded in Freescale i.MX93 SoC. Some configurations
15 and extensions to them are controlled by i.MX93 media blk-ctrl.
18 - $ref: snps,dw-mipi-dsi.yaml#
22 const: fsl,imx93-mipi-dsi
26 - description: apb clock
27 - description: pixel clock
28 - description: PHY configuration clock
29 - description: PHY reference clock
42 $ref: /schemas/types.yaml#/definitions/phandle
44 i.MX93 media blk-ctrl, as a syscon, controls pixel component bit map
45 configurations from LCDIF display controller to the MIPI DSI host
46 controller and MIPI DPHY PLL related configurations through PLL SoC
58 unevaluatedProperties: false
62 #include <dt-bindings/clock/imx93-clock.h>
63 #include <dt-bindings/gpio/gpio.h>
64 #include <dt-bindings/interrupt-controller/arm-gic.h>
65 #include <dt-bindings/power/fsl,imx93-power.h>
68 compatible = "fsl,imx93-mipi-dsi";
69 reg = <0x4ae10000 0x10000>;
70 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
71 clocks = <&clk IMX93_CLK_MIPI_DSI_GATE>,
72 <&clk IMX93_CLK_MEDIA_DISP_PIX>,
73 <&clk IMX93_CLK_MIPI_PHY_CFG>,
75 clock-names = "pclk", "pix", "phy_cfg", "phy_ref";
76 fsl,media-blk-ctrl = <&media_blk_ctrl>;
77 power-domains = <&media_blk_ctrl IMX93_MEDIABLK_PD_MIPI_DSI>;
82 compatible = "raydium,rm67191";
84 reset-gpios = <&adp5585gpio 6 GPIO_ACTIVE_LOW>;
90 remote-endpoint = <&dsi_out>;
102 dsi_to_lcdif: endpoint {
103 remote-endpoint = <&lcdif_to_dsi>;
111 remote-endpoint = <&panel_in>;