1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-pixel-combiner.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX8qm/qxp Pixel Combiner
10 - Liu Ying <victor.liu@nxp.com>
13 The Freescale i.MX8qm/qxp Pixel Combiner takes two output streams from a
14 single display controller and manipulates the two streams to support a number
15 of modes(bypass, pixel combine, YUV444 to YUV422, split_RGB) configured as
16 either one screen, two screens, or virtual screens. The pixel combiner is
17 also responsible for generating some of the control signals for the pixel link
23 - fsl,imx8qm-pixel-combiner
24 - fsl,imx8qxp-pixel-combiner
47 description: Represents a display stream of pixel combiner.
57 description: The display stream index.
61 $ref: /schemas/graph.yaml#/properties/port
62 description: Input endpoint of the display stream.
65 $ref: /schemas/graph.yaml#/properties/port
66 description: Output endpoint of the display stream.
75 additionalProperties: false
86 additionalProperties: false
90 #include <dt-bindings/clock/imx8-lpcg.h>
91 #include <dt-bindings/firmware/imx/rsrc.h>
92 pixel-combiner@56020000 {
93 compatible = "fsl,imx8qxp-pixel-combiner";
96 reg = <0x56020000 0x10000>;
97 clocks = <&dc0_pixel_combiner_lpcg IMX_LPCG_CLK_4>;
99 power-domains = <&pd IMX_SC_R_DC_0>;
102 #address-cells = <1>;
109 dc0_pixel_combiner_ch0_dc0_dpu_disp0: endpoint {
110 remote-endpoint = <&dc0_dpu_disp0_dc0_pixel_combiner_ch0>;
117 dc0_pixel_combiner_ch0_dc0_pixel_link0: endpoint {
118 remote-endpoint = <&dc0_pixel_link0_dc0_pixel_combiner_ch0>;
124 #address-cells = <1>;
131 dc0_pixel_combiner_ch1_dc0_dpu_disp1: endpoint {
132 remote-endpoint = <&dc0_dpu_disp1_dc0_pixel_combiner_ch1>;
139 dc0_pixel_combiner_ch1_dc0_pixel_link1: endpoint {
140 remote-endpoint = <&dc0_pixel_link1_dc0_pixel_combiner_ch1>;