1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/display/arm,malidp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Arm Mali Display Processor (Mali-DP) binding
10 - Liviu Dudau <Liviu.Dudau@arm.com>
11 - Andre Przywara <andre.przywara@arm.com>
14 The following bindings apply to a family of Display Processors sold as
15 licensable IP by ARM Ltd. The bindings describe the Mali DP500, DP550 and
16 DP650 processors that offer multiple composition layers, support for
17 rotation and scaling output.
32 The interrupt used by the Display Engine (DE). Can be shared with
33 the interrupt for the Scaling Engine (SE), but it will have to be
36 The interrupt used by the Scaling Engine (SE). Can be shared with
37 the interrupt for the Display Engine (DE), but it will have to be
54 - description: the pixel clock feeding the output PLL of the processor
55 - description: the main processor clock
56 - description: the AXI interface clock
57 - description: the APB interface clock
62 Phandle to a node describing memory to be used for the framebuffer.
63 If not present, the framebuffer may be located anywhere in memory.
65 arm,malidp-output-port-lines:
66 $ref: /schemas/types.yaml#/definitions/uint8-array
68 Number of output lines/bits for each colour channel.
70 - description: number of output lines for the red channel (R)
71 - description: number of output lines for the green channel (G)
72 - description: number of output lines for the blue channel (B)
74 arm,malidp-arqos-high-level:
75 $ref: /schemas/types.yaml#/definitions/uint32
77 integer describing the ARQoS levels of DP500's QoS signaling
79 arm,malidp-arqos-value:
80 $ref: /schemas/types.yaml#/definitions/uint32
82 Quality-of-Service value for the display engine FIFOs, to write
83 into the RQOS register of the DP500.
84 See the ARM Mali-DP500 TRM for details on the encoding.
85 If omitted, the RQOS register will not be changed.
88 $ref: /schemas/graph.yaml#/properties/port
89 unevaluatedProperties: false
91 Output endpoint of the controller, connecting the LCD panel signals.
93 additionalProperties: false
103 - arm,malidp-output-port-lines
107 dp0: malidp@6f200000 {
108 compatible = "arm,mali-dp650";
109 reg = <0x6f200000 0x20000>;
110 memory-region = <&display_reserved>;
111 interrupts = <168>, <168>;
112 interrupt-names = "DE", "SE";
113 clocks = <&oscclk2>, <&fpgaosc0>, <&fpgaosc1>, <&fpgaosc1>;
114 clock-names = "pxlclk", "mclk", "aclk", "pclk";
115 arm,malidp-output-port-lines = /bits/ 8 <8 8 8>;
116 arm,malidp-arqos-high-level = <0xd000d000>;
119 dp0_output: endpoint {
120 remote-endpoint = <&tda998x_2_input>;