1 # SPDX-License-Identifier: GPL-2.0
4 $id: http://devicetree.org/schemas/display/allwinner,sun8i-a83t-dw-hdmi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A83t DWC HDMI TX Encoder Device Tree Bindings
10 The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller
11 IP with Allwinner\'s own PHY IP. It supports audio and video outputs
14 These DT bindings follow the Synopsys DWC HDMI TX bindings defined
15 in bridge/synopsys,dw-hdmi.yaml with the following device-specific
19 - Chen-Yu Tsai <wens@csie.org>
20 - Maxime Ripard <mripard@kernel.org>
28 - const: allwinner,sun8i-a83t-dw-hdmi
29 - const: allwinner,sun50i-h6-dw-hdmi
33 - allwinner,sun8i-h3-dw-hdmi
34 - allwinner,sun8i-r40-dw-hdmi
35 - allwinner,sun50i-a64-dw-hdmi
36 - const: allwinner,sun8i-a83t-dw-hdmi
50 - description: Bus Clock
51 - description: Register Clock
52 - description: TMDS Clock
53 - description: HDMI CEC Clock
54 - description: HDCP Clock
55 - description: HDCP Bus Clock
70 - description: HDMI Controller Reset
71 - description: HDCP Reset
82 Phandle to the DWC HDMI PHY.
89 The VCC power supply of the controller
92 $ref: /schemas/graph.yaml#/properties/ports
96 $ref: /schemas/graph.yaml#/properties/port
98 Input endpoints of the controller. Usually the associated
102 $ref: /schemas/graph.yaml#/properties/port
104 Output endpoints of the controller. Usually an HDMI
129 - allwinner,sun50i-h6-dw-hdmi
146 additionalProperties: false
150 #include <dt-bindings/interrupt-controller/arm-gic.h>
153 * This comes from the clock/sun8i-a83t-ccu.h and
154 * reset/sun8i-a83t-ccu.h headers, but we can't include them since
155 * it would trigger a bunch of warnings for redefinitions of
156 * symbols with the other example.
158 #define CLK_BUS_HDMI 39
160 #define CLK_HDMI_SLOW 94
161 #define RST_BUS_HDMI1 26
164 compatible = "allwinner,sun8i-a83t-dw-hdmi";
165 reg = <0x01ee0000 0x10000>;
167 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
168 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>,
170 clock-names = "iahb", "isfr", "tmds";
171 resets = <&ccu RST_BUS_HDMI1>;
172 reset-names = "ctrl";
175 pinctrl-names = "default";
176 pinctrl-0 = <&hdmi_pins>;
180 #address-cells = <1>;
187 remote-endpoint = <&tcon1_out_hdmi>;
197 /* Cleanup after ourselves */
203 #include <dt-bindings/interrupt-controller/arm-gic.h>
206 * This comes from the clock/sun50i-h6-ccu.h and
207 * reset/sun50i-h6-ccu.h headers, but we can't include them since
208 * it would trigger a bunch of warnings for redefinitions of
209 * symbols with the other example.
211 #define CLK_BUS_HDMI 126
212 #define CLK_BUS_HDCP 137
214 #define CLK_HDMI_SLOW 124
215 #define CLK_HDMI_CEC 125
217 #define RST_BUS_HDMI_SUB 57
218 #define RST_BUS_HDCP 62
221 compatible = "allwinner,sun50i-h6-dw-hdmi";
222 reg = <0x06000000 0x10000>;
224 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
225 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>,
226 <&ccu CLK_HDMI>, <&ccu CLK_HDMI_CEC>,
227 <&ccu CLK_HDCP>, <&ccu CLK_BUS_HDCP>;
228 clock-names = "iahb", "isfr", "tmds", "cec", "hdcp",
230 resets = <&ccu RST_BUS_HDMI_SUB>, <&ccu RST_BUS_HDCP>;
231 reset-names = "ctrl", "hdcp";
234 pinctrl-names = "default";
235 pinctrl-0 = <&hdmi_pins>;
239 #address-cells = <1>;
246 remote-endpoint = <&tcon_top_hdmi_out_hdmi>;