1 Binding for a ST pll clock driver.
3 This binding uses the common clock binding[1].
4 Base address is located to the parent node. See clock binding[2]
6 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
7 [2] Documentation/devicetree/bindings/clock/st/st,clkgen.txt
11 - compatible : shall be:
17 "st,stih407-clkgen-plla9"
18 "st,stih418-clkgen-plla9"
20 - #clock-cells : From common clock binding; shall be set to 1.
22 - clocks : From common clock binding
24 - clock-output-names : From common clock binding.
29 compatible = "st,clkgen-c32";
30 reg = <0x92b0000 0xffff>;
32 clockgen_a9_pll: clockgen-a9-pll {
34 compatible = "st,stih407-clkgen-plla9";
36 clocks = <&clk_sysin>;
38 clock-output-names = "clockgen-a9-pll-odf";