1 * Rockchip RK3288 Clock and Reset Unit
3 The RK3288 clock controller generates and supplies clock to various
4 controllers within the SoC and also implements a reset controller for SoC
7 A revision of this SoC is available: rk3288w. The clock tree is a bit
8 different so another dt-compatible is available. Noticed that it is only
9 setting the difference but there is no automatic revision detection. This
10 should be performed by bootloaders.
14 - compatible: should be "rockchip,rk3288-cru" or "rockchip,rk3288w-cru" in
15 case of this revision of Rockchip rk3288.
16 - reg: physical base address of the controller and length of memory mapped
18 - #clock-cells: should be 1.
19 - #reset-cells: should be 1.
23 - rockchip,grf: phandle to the syscon managing the "general register files"
24 If missing pll rates are not changeable, due to the missing pll lock status.
26 Each clock is assigned an identifier and client nodes can use this identifier
27 to specify the clock which they consume. All available clocks are defined as
28 preprocessor macros in the dt-bindings/clock/rk3288-cru.h headers and can be
29 used in device tree sources. Similar macros exist for the reset sources in
34 There are several clocks that are generated outside the SoC. It is expected
35 that they are defined using standard clock bindings with following
37 - "xin24m" - crystal input - required,
38 - "xin32k" - rtc clock - optional,
39 - "ext_i2s" - external I2S clock - optional,
40 - "ext_hsadc" - external HSADC clock - optional,
41 - "ext_edp_24m" - external display port clock - optional,
42 - "ext_vip" - external VIP clock - optional,
43 - "ext_isp" - external ISP clock - optional,
44 - "ext_jtag" - external JTAG clock - optional
46 Example: Clock controller node:
49 compatible = "rockchip,rk3188-cru";
50 reg = <0x20000000 0x1000>;
51 rockchip,grf = <&grf>;
57 Example: UART controller node that consumes the clock generated by the clock
60 uart0: serial@10124000 {
61 compatible = "snps,dw-apb-uart";
62 reg = <0x10124000 0x400>;
63 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
66 clocks = <&cru SCLK_UART0>;