1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/clock/renesas,cpg-mstp-clocks.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas Clock Pulse Generator (CPG) Module Stop (MSTP) Clocks
10 - Geert Uytterhoeven <geert+renesas@glider.be>
13 The Clock Pulse Generator (CPG) can gate SoC device clocks. The gates are
14 organized in groups of up to 32 gates.
16 This device tree binding describes a single 32 gate clocks group per node.
17 Clocks are referenced by user nodes by the Module Stop (MSTP) node phandle
18 and the clock index in the group, from 0 to 31.
24 - renesas,r7s72100-mstp-clocks # RZ/A1
25 - renesas,r8a73a4-mstp-clocks # R-Mobile APE6
26 - renesas,r8a7740-mstp-clocks # R-Mobile A1
27 - renesas,r8a7778-mstp-clocks # R-Car M1
28 - renesas,r8a7779-mstp-clocks # R-Car H1
29 - renesas,sh73a0-mstp-clocks # SH-Mobile AG5
30 - const: renesas,cpg-mstp-clocks
35 - description: Module Stop Control Register (MSTPCR)
36 - description: Module Stop Status Register (MSTPSR)
61 additionalProperties: false
65 #include <dt-bindings/clock/r8a73a4-clock.h>
66 mstp2_clks: mstp2_clks@e6150138 {
67 compatible = "renesas,r8a73a4-mstp-clocks",
68 "renesas,cpg-mstp-clocks";
69 reg = <0xe6150138 4>, <0xe6150040 4>;
70 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
71 <&mp_clk>, <&cpg_clocks R8A73A4_CLK_HP>;
74 R8A73A4_CLK_SCIFA0 R8A73A4_CLK_SCIFA1
75 R8A73A4_CLK_SCIFB0 R8A73A4_CLK_SCIFB1
76 R8A73A4_CLK_SCIFB2 R8A73A4_CLK_SCIFB3
80 "scifa0", "scifa1", "scifb0", "scifb1", "scifb2", "scifb3",