1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/clock/qcom,x1e80100-gcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Global Clock & Reset Controller on X1E80100
10 - Rajendra Nayak <quic_rjendra@quicinc.com>
13 Qualcomm global clock control module provides the clocks, resets and power
16 See also:: include/dt-bindings/clock/qcom,x1e80100-gcc.h
20 const: qcom,x1e80100-gcc
24 - description: Board XO source
25 - description: Sleep clock source
26 - description: PCIe 3 pipe clock
27 - description: PCIe 4 pipe clock
28 - description: PCIe 5 pipe clock
29 - description: PCIe 6a pipe clock
30 - description: PCIe 6b pipe clock
31 - description: USB QMP Phy 0 clock source
32 - description: USB QMP Phy 1 clock source
33 - description: USB QMP Phy 2 clock source
37 A phandle and PM domain specifier for the CX power domain.
46 - $ref: qcom,gcc.yaml#
48 unevaluatedProperties: false
52 #include <dt-bindings/power/qcom,rpmhpd.h>
53 clock-controller@100000 {
54 compatible = "qcom,x1e80100-gcc";
55 reg = <0x00100000 0x200000>;
56 clocks = <&bi_tcxo_div2>,
63 <&usb_1_ss0_qmpphy 0>,
64 <&usb_1_ss1_qmpphy 1>,
65 <&usb_1_ss2_qmpphy 2>;
66 power-domains = <&rpmhpd RPMHPD_CX>;
69 #power-domain-cells = <1>;