Documentation/devicetree/bindings/clock/qcom,gpucc.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/clock/qcom,gpucc.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Qualcomm Graphics Clock & Reset Controller Binding
   8
   9 maintainers:
  10   - Taniya Das <tdas@codeaurora.org>
  11
  12 description: |
  13   Qualcomm graphics clock control module which supports the clocks, resets and
  14   power domains on Qualcomm SoCs.
  15
  16   See also:
  17     dt-bindings/clock/qcom,gpucc-sdm845.h
  18     dt-bindings/clock/qcom,gpucc-sc7180.h
  19     dt-bindings/clock/qcom,gpucc-sc7280.h
  20     dt-bindings/clock/qcom,gpucc-sm6350.h
  21     dt-bindings/clock/qcom,gpucc-sm8150.h
  22     dt-bindings/clock/qcom,gpucc-sm8250.h
  23
  24 properties:
  25   compatible:
  26     enum:
  27       - qcom,sdm845-gpucc
  28       - qcom,sc7180-gpucc
  29       - qcom,sc7280-gpucc
  30       - qcom,sc8180x-gpucc
  31       - qcom,sm6350-gpucc
  32       - qcom,sm8150-gpucc
  33       - qcom,sm8250-gpucc
  34
  35   clocks:
  36     items:
  37       - description: Board XO source
  38       - description: GPLL0 main branch source
  39       - description: GPLL0 div branch source
  40
  41   clock-names:
  42     items:
  43       - const: bi_tcxo
  44       - const: gcc_gpu_gpll0_clk_src
  45       - const: gcc_gpu_gpll0_div_clk_src
  46
  47   '#clock-cells':
  48     const: 1
  49
  50   '#reset-cells':
  51     const: 1
  52
  53   '#power-domain-cells':
  54     const: 1
  55
  56   reg:
  57     maxItems: 1
  58
  59 required:
  60   - compatible
  61   - reg
  62   - clocks
  63   - clock-names
  64   - '#clock-cells'
  65   - '#reset-cells'
  66   - '#power-domain-cells'
  67
  68 additionalProperties: false
  69
  70 examples:
  71   - |
  72     #include <dt-bindings/clock/qcom,gcc-sdm845.h>
  73     #include <dt-bindings/clock/qcom,rpmh.h>
  74     clock-controller@5090000 {
  75       compatible = "qcom,sdm845-gpucc";
  76       reg = <0x05090000 0x9000>;
  77       clocks = <&rpmhcc RPMH_CXO_CLK>,
  78                <&gcc GCC_GPU_GPLL0_CLK_SRC>,
  79                <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
  80       clock-names = "bi_tcxo",
  81                     "gcc_gpu_gpll0_clk_src",
  82                     "gcc_gpu_gpll0_div_clk_src";
  83       #clock-cells = <1>;
  84       #reset-cells = <1>;
  85       #power-domain-cells = <1>;
  86     };
  87 ...