Documentation/devicetree/bindings/clock/qcom,gcc-sdx65.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/clock/qcom,gcc-sdx65.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Qualcomm Global Clock & Reset Controller Binding for SDX65
   8
   9 maintainers:
  10   - Vamsi krishna Lanka <quic_vamslank@quicinc.com>
  11
  12 description: |
  13   Qualcomm global clock control module which supports the clocks, resets and
  14   power domains on SDX65
  15
  16   See also:
  17   - dt-bindings/clock/qcom,gcc-sdx65.h
  18
  19 properties:
  20   compatible:
  21     const: qcom,gcc-sdx65
  22
  23   clocks:
  24     items:
  25       - description: Board XO source
  26       - description: Board active XO source
  27       - description: Sleep clock source
  28       - description: PCIE Pipe clock source
  29       - description: USB3 phy wrapper pipe clock source
  30       - description: PLL test clock source (Optional clock)
  31     minItems: 5
  32
  33   clock-names:
  34     items:
  35       - const: bi_tcxo
  36       - const: bi_tcxo_ao
  37       - const: sleep_clk
  38       - const: pcie_pipe_clk
  39       - const: usb3_phy_wrapper_gcc_usb30_pipe_clk
  40       - const: core_bi_pll_test_se # Optional clock
  41     minItems: 5
  42
  43 required:
  44   - compatible
  45   - clocks
  46   - clock-names
  47
  48 allOf:
  49   - $ref: qcom,gcc.yaml#
  50
  51 unevaluatedProperties: false
  52
  53 examples:
  54   - |
  55     #include <dt-bindings/clock/qcom,rpmh.h>
  56     clock-controller@100000 {
  57       compatible = "qcom,gcc-sdx65";
  58       reg = <0x100000 0x1f7400>;
  59       clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>,
  60                <&pcie_pipe_clk>, <&usb3_phy_wrapper_gcc_usb30_pipe_clk>, <&pll_test_clk>;
  61       clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk",
  62                     "pcie_pipe_clk", "usb3_phy_wrapper_gcc_usb30_pipe_clk", "core_bi_pll_test_se";
  63       #clock-cells = <1>;
  64       #reset-cells = <1>;
  65       #power-domain-cells = <1>;
  66     };
  67 ...