Documentation/devicetree/bindings/clock/qcom,dispcc.yaml

   1 # SPDX-License-Identifier: GPL-2.0-only
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/bindings/clock/qcom,dispcc.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Qualcomm Display Clock & Reset Controller Binding
   8
   9 maintainers:
  10   - Taniya Das <tdas@codeaurora.org>
  11
  12 description: |
  13   Qualcomm display clock control module which supports the clocks, resets and
  14   power domains.
  15
  16 properties:
  17   compatible:
  18     enum:
  19       - qcom,sc7180-dispcc
  20       - qcom,sdm845-dispcc
  21
  22   clocks:
  23     minItems: 1
  24     maxItems: 2
  25     items:
  26       - description: Board XO source
  27       - description: GPLL0 source from GCC
  28
  29   clock-names:
  30     items:
  31       - const: xo
  32       - const: gpll0
  33
  34   '#clock-cells':
  35     const: 1
  36
  37   '#reset-cells':
  38     const: 1
  39
  40   '#power-domain-cells':
  41     const: 1
  42
  43   reg:
  44     maxItems: 1
  45
  46 required:
  47   - compatible
  48   - reg
  49   - clocks
  50   - clock-names
  51   - '#clock-cells'
  52   - '#reset-cells'
  53   - '#power-domain-cells'
  54
  55 examples:
  56   # Example of DISPCC with clock node properties for SDM845:
  57   - |
  58     clock-controller@af00000 {
  59       compatible = "qcom,sdm845-dispcc";
  60       reg = <0xaf00000 0x10000>;
  61       clocks = <&rpmhcc 0>, <&gcc 24>;
  62       clock-names = "xo", "gpll0";
  63       #clock-cells = <1>;
  64       #reset-cells = <1>;
  65       #power-domain-cells = <1>;
  66      };
  67 ...