1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/clock/nvidia,tegra124-car.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra Clock and Reset Controller
10 - Jon Hunter <jonathanh@nvidia.com>
11 - Thierry Reding <thierry.reding@gmail.com>
14 The Clock and Reset (CAR) is the HW module responsible for muxing and gating
15 Tegra's clocks, and setting their rates. It comprises CLKGEN and RSTGEN units.
17 CLKGEN provides the registers to program the PLLs. It controls most of
18 the clock source programming and most of the clock dividers.
20 CLKGEN input signals include the external clock for the reference frequency
21 (12 MHz, 26 MHz) and the external clock for the Real Time Clock (32.768 KHz).
23 Outputs from CLKGEN are inputs clock of the h/w blocks in the Tegra system.
25 RSTGEN provides the registers needed to control resetting of each block in
30 const: nvidia,tegra124-car
41 nvidia,external-memory-controller:
42 $ref: /schemas/types.yaml#/definitions/phandle
44 phandle of the external memory controller node
47 "^emc-timings-[0-9]+$":
51 $ref: /schemas/types.yaml#/definitions/uint32
53 value of the RAM_CODE field in the PMC_STRAPPING_OPT_A register that
54 this timing set is used for
62 external memory clock rate in Hz
66 nvidia,parent-clock-frequency:
67 $ref: /schemas/types.yaml#/definitions/uint32
69 rate of parent clock in Hz
75 - description: parent clock of EMC
83 - nvidia,parent-clock-frequency
87 additionalProperties: false
89 additionalProperties: false
97 additionalProperties: false
101 #include <dt-bindings/clock/tegra124-car.h>
103 car: clock-controller@60006000 {
104 compatible = "nvidia,tegra124-car";
105 reg = <0x60006000 0x1000>;
110 usb-controller@c5004000 {
111 compatible = "nvidia,tegra20-ehci";
112 reg = <0xc5004000 0x4000>;
113 clocks = <&car TEGRA124_CLK_USB2>;
114 resets = <&car TEGRA124_CLK_USB2>;