Documentation/devicetree/bindings/clock/microchip,sparx5-dpll.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/clock/microchip,sparx5-dpll.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Microchip Sparx5 DPLL Clock
   8
   9 maintainers:
  10   - Lars Povlsen <lars.povlsen@microchip.com>
  11
  12 description: |
  13   The Sparx5 DPLL clock controller generates and supplies clock to
  14   various peripherals within the SoC.
  15
  16 properties:
  17   compatible:
  18     const: microchip,sparx5-dpll
  19
  20   reg:
  21     maxItems: 1
  22
  23   clocks:
  24     maxItems: 1
  25
  26   '#clock-cells':
  27     const: 1
  28
  29 required:
  30   - compatible
  31   - reg
  32   - clocks
  33   - '#clock-cells'
  34
  35 additionalProperties: false
  36
  37 examples:
  38   # Clock provider for eMMC:
  39   - |
  40     lcpll_clk: lcpll-clk {
  41         compatible = "fixed-clock";
  42         #clock-cells = <0>;
  43         clock-frequency = <2500000000>;
  44     };
  45     clks: clock-controller@61110000c {
  46         compatible = "microchip,sparx5-dpll";
  47         #clock-cells = <1>;
  48         clocks = <&lcpll_clk>;
  49         reg = <0x1110000c 0x24>;
  50     };
  51
  52 ...