1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/clock/microchip,sparx5-dpll.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip Sparx5 DPLL Clock
10 - Lars Povlsen <lars.povlsen@microchip.com>
13 The Sparx5 DPLL clock controller generates and supplies clock to
14 various peripherals within the SoC.
18 const: microchip,sparx5-dpll
35 additionalProperties: false
38 # Clock provider for eMMC:
40 lcpll_clk: lcpll-clk {
41 compatible = "fixed-clock";
43 clock-frequency = <2500000000>;
45 clks: clock-controller@61110000c {
46 compatible = "microchip,sparx5-dpll";
48 clocks = <&lcpll_clk>;
49 reg = <0x1110000c 0x24>;