Merge branch 'x86/entry' into ras/core
[linux-2.6-microblaze.git] / Documentation / devicetree / bindings / clock / imx6sx-clock.yaml
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/clock/imx6sx-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: Clock bindings for Freescale i.MX6 SoloX
8
9 maintainers:
10   - Anson Huang <Anson.Huang@nxp.com>
11
12 properties:
13   compatible:
14     const: fsl,imx6sx-ccm
15
16   reg:
17     maxItems: 1
18
19   interrupts:
20     description: CCM provides 2 interrupt requests, request 1 is to generate
21       interrupt for frequency or mux change, request 2 is to generate
22       interrupt for oscillator read or PLL lock.
23     items:
24       - description: CCM interrupt request 1
25       - description: CCM interrupt request 2
26     maxItems: 2
27
28   '#clock-cells':
29     const: 1
30
31   clocks:
32     items:
33       - description: 32k osc
34       - description: 24m osc
35       - description: ipp_di0 clock input
36       - description: ipp_di1 clock input
37       - description: anaclk1 clock input
38       - description: anaclk2 clock input
39
40   clock-names:
41     items:
42       - const: ckil
43       - const: osc
44       - const: ipp_di0
45       - const: ipp_di1
46       - const: anaclk1
47       - const: anaclk2
48
49 required:
50   - compatible
51   - reg
52   - interrupts
53   - '#clock-cells'
54   - clocks
55   - clock-names
56
57 examples:
58   # Clock Control Module node:
59   - |
60     #include <dt-bindings/interrupt-controller/arm-gic.h>
61
62     clock-controller@20c4000 {
63         compatible = "fsl,imx6sx-ccm";
64         reg = <0x020c4000 0x4000>;
65         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
66                      <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
67         #clock-cells = <1>;
68         clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>, <&anaclk1>, <&anaclk2>;
69         clock-names = "ckil", "osc", "ipp_di0", "ipp_di1", "anaclk1", "anaclk2";
70     };