1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/clock/idt,versaclock5.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Binding for IDT VersaClock 5 and 6 programmable I2C clock generators
10 The IDT VersaClock 5 and VersaClock 6 are programmable I2C
11 clock generators providing from 3 to 12 output clocks.
13 When referencing the provided clock in the DT using phandle and clock
14 specifier, the following mapping applies:
34 - Luca Ceresoli <luca@lucaceresoli.net>
47 description: I2C device address
62 idt,xtal-load-femtofarads:
65 description: Optional load capacitor for XTAL1 and XTAL2
71 Description of one of the outputs (OUT1..OUT4). See "Clock1 Output
72 Configuration" in the Versaclock 5/6/6E Family Register Description
73 and Programming Guide.
77 The output drive mode. Values defined in dt-bindings/clk/versaclock.h
78 $ref: /schemas/types.yaml#/definitions/uint32
81 idt,voltage-microvolt:
82 description: The output drive voltage.
83 enum: [ 1800000, 2500000, 3300000 ]
85 description: The Slew rate control for CMOS single-ended.
86 enum: [ 80, 85, 90, 100 ]
87 additionalProperties: false
102 # Devices with builtin crystal + optional external input
109 # Devices without builtin crystal
114 additionalProperties: false
118 #include <dt-bindings/clk/versaclock.h>
120 /* 25MHz reference crystal */
122 compatible = "fixed-clock";
124 clock-frequency = <25000000>;
129 #address-cells = <1>;
132 /* IDT 5P49V5923 I2C clock generator */
133 vc5: clock-generator@6a {
134 compatible = "idt,5p49v5923";
138 /* Connect XIN input to 25MHz reference */
143 idt,mode = <VC5_CMOSD>;
144 idt,voltage-microvolt = <1800000>;
145 idt,slew-percent = <80>;
149 idt,mode = <VC5_LVDS>;
154 /* Consumer referencing the 5P49V5923 pin OUT1 */