1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/clock/idt,versaclock5.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Binding for IDT VersaClock 5 and 6 programmable I2C clock generators
10 The IDT VersaClock 5 and VersaClock 6 are programmable I2C
11 clock generators providing from 3 to 12 output clocks.
13 When referencing the provided clock in the DT using phandle and clock
14 specifier, the following mapping applies:
34 - Luca Ceresoli <luca@lucaceresoli.net>
47 description: I2C device address
62 idt,xtal-load-femtofarads:
63 $ref: /schemas/types.yaml#/definitions/uint32
66 description: Optional load capacitor for XTAL1 and XTAL2
72 Description of one of the outputs (OUT1..OUT4). See "Clock1 Output
73 Configuration" in the Versaclock 5/6/6E Family Register Description
74 and Programming Guide.
78 The output drive mode. Values defined in dt-bindings/clk/versaclock.h
79 $ref: /schemas/types.yaml#/definitions/uint32
82 idt,voltage-microvolt:
83 description: The output drive voltage.
84 enum: [ 1800000, 2500000, 3300000 ]
86 description: The Slew rate control for CMOS single-ended.
87 $ref: /schemas/types.yaml#/definitions/uint32
88 enum: [ 80, 85, 90, 100 ]
103 # Devices with builtin crystal + optional external input
110 # Devices without builtin crystal
115 additionalProperties: false
119 #include <dt-bindings/clk/versaclock.h>
121 /* 25MHz reference crystal */
123 compatible = "fixed-clock";
125 clock-frequency = <25000000>;
130 #address-cells = <1>;
133 /* IDT 5P49V5923 I2C clock generator */
134 vc5: clock-generator@6a {
135 compatible = "idt,5p49v5923";
139 /* Connect XIN input to 25MHz reference */
144 idt,drive-mode = <VC5_CMOSD>;
145 idt,voltage-microvolts = <1800000>;
146 idt,slew-percent = <80>;
150 idt,drive-mode = <VC5_LVDS>;
155 /* Consumer referencing the 5P49V5923 pin OUT1 */