1 # SPDX-License-Identifier: GPL-2.0
4 $id: http://devicetree.org/schemas/arm/cpus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM CPUs bindings
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
13 The device tree allows to describe the layout of CPUs in a system through
14 the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
15 defining properties for every cpu.
17 Bindings for CPU nodes follow the Devicetree Specification, available from:
19 https://www.devicetree.org/specifications/
21 with updates for 32-bit and 64-bit ARM systems provided in this document.
23 ================================
24 Convention used in this document
25 ================================
27 This document follows the conventions described in the Devicetree
28 Specification, with the addition:
30 - square brackets define bitfields, eg reg[7:0] value of the bitfield in
31 the reg property contained in bits 7 down to 0
33 =====================================
34 cpus and cpu node bindings definition
35 =====================================
37 The ARM architecture, in accordance with the Devicetree Specification,
38 requires the cpus and cpu nodes to be present and contain the properties
45 Usage and definition depend on ARM architecture version and
48 On uniprocessor ARM architectures previous to v7
49 this property is required and must be set to 0.
51 On ARM 11 MPcore based systems this property is
52 required and matches the CPUID[11:0] register bits.
54 Bits [11:0] in the reg cell must be set to
55 bits [11:0] in CPU ID register.
57 All other bits in the reg cell must be set to 0.
59 On 32-bit ARM v7 or later systems this property is
60 required and matches the CPU MPIDR[23:0] register
63 Bits [23:0] in the reg cell must be set to
66 All other bits in the reg cell must be set to 0.
68 On ARM v8 64-bit systems this property is required
69 and matches the MPIDR_EL1 register affinity bits.
71 * If cpus node's #address-cells property is set to 2
73 The first reg cell bits [7:0] must be set to
74 bits [39:32] of MPIDR_EL1.
76 The second reg cell bits [23:0] must be set to
77 bits [23:0] of MPIDR_EL1.
79 * If cpus node's #address-cells property is set to 1
81 The reg cell bits [23:0] must be set to bits [23:0]
84 All other bits in the reg cells must be set to 0.
118 - arm,armv8 # Only for s/w models
162 - nvidia,tegra132-denver
163 - nvidia,tegra186-denver
164 - nvidia,tegra194-carmel
176 $ref: '/schemas/types.yaml#/definitions/string'
178 # On ARM v8 64-bit this property is required
182 # On ARM 32-bit systems this property is optional
185 - allwinner,sun6i-a31
186 - allwinner,sun8i-a23
187 - allwinner,sun9i-a80-smp
188 - allwinner,sun8i-a83t-smp
190 - amlogic,meson8b-smp
193 - brcm,bcm11351-cpu-method
199 - marvell,armada-375-smp
200 - marvell,armada-380-smp
201 - marvell,armada-390-smp
202 - marvell,armada-xp-smp
203 - marvell,98dx3236-smp
205 - mediatek,mt6589-smp
206 - mediatek,mt81xx-tz-smp
211 - renesas,r9a06g032-smp
212 - rockchip,rk3036-smp
213 - rockchip,rk3066-smp
214 - socionext,milbeaut-m10v-smp
220 $ref: '/schemas/types.yaml#/definitions/uint64'
223 Required for systems that have an "enable-method"
224 property value of "spin-table".
225 On ARM v8 64-bit systems must be a two cell
226 property identifying a 64-bit zero-initialised
230 $ref: '/schemas/types.yaml#/definitions/phandle-array'
232 List of phandles to idle state nodes supported
233 by this cpu (see ./idle-states.yaml).
236 $ref: '/schemas/types.yaml#/definitions/uint32'
238 u32 value representing CPU capacity (see ./cpu-capacity.txt) in
239 DMIPS/MHz, relative to highest capacity-dmips-mhz
242 dynamic-power-coefficient:
243 $ref: '/schemas/types.yaml#/definitions/uint32'
245 A u32 value that represents the running time dynamic
246 power coefficient in units of uW/MHz/V^2. The
247 coefficient can either be calculated from power
248 measurements or derived by analysis.
250 The dynamic power consumption of the CPU is
251 proportional to the square of the Voltage (V) and
252 the clock frequency (f). The coefficient is used to
253 calculate the dynamic power as below -
255 Pdyn = dynamic-power-coefficient * V^2 * f
257 where voltage is in V, frequency is in MHz.
260 $ref: '/schemas/types.yaml#/definitions/phandle-array'
262 List of phandles and PM domain specifiers, as defined by bindings of the
263 PM domain provider (see also ../power_domain.txt).
266 $ref: '/schemas/types.yaml#/definitions/string-array'
268 A list of power domain name strings sorted in the same order as the
269 power-domains property.
271 For PSCI based platforms, the name corresponding to the index of the PSCI
272 PM domain provider, must be "psci".
275 $ref: '/schemas/types.yaml#/definitions/phandle'
277 Specifies the SAW* node associated with this CPU.
279 Required for systems that have an "enable-method" property
280 value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2"
282 * arm/msm/qcom,saw2.txt
285 $ref: '/schemas/types.yaml#/definitions/phandle'
287 Specifies the ACC* node associated with this CPU.
289 Required for systems that have an "enable-method" property
290 value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2"
292 * arm/msm/qcom,kpss-acc.txt
295 $ref: '/schemas/types.yaml#/definitions/phandle'
297 Specifies the syscon node controlling the cpu core power domains.
299 Optional for systems that have an "enable-method"
300 property value of "rockchip,rk3066-smp"
301 While optional, it is the preferred way to get access to
302 the cpu-core power-domains.
305 $ref: '/schemas/types.yaml#/definitions/uint32'
307 Required for systems that have an "enable-method" property value of
308 "brcm,bcm11351-cpu-method", "brcm,bcm23550" or "brcm,bcm-nsp-smp".
310 This includes the following SoCs: |
311 BCM11130, BCM11140, BCM11351, BCM28145, BCM28155, BCM21664, BCM23550
312 BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312
314 The secondary-boot-reg property is a u32 value that specifies the
315 physical address of the register used to request the ROM holding pen
316 code release a secondary CPU. The value written to the register is
317 formed by encoding the target CPU id into the low bits of the
318 physical start address it should jump to.
321 # If the enable-method property contains one of those values
326 - brcm,bcm11351-cpu-method
329 # and if enable-method is present
343 rockchip,pmu: [enable-method]
345 additionalProperties: true
351 #address-cells = <1>;
355 compatible = "arm,cortex-a15";
361 compatible = "arm,cortex-a15";
367 compatible = "arm,cortex-a7";
373 compatible = "arm,cortex-a7";
379 // Example 2 (Cortex-A8 uniprocessor 32-bit system):
382 #address-cells = <1>;
386 compatible = "arm,cortex-a8";
392 // Example 3 (ARM 926EJ-S uniprocessor 32-bit system):
395 #address-cells = <1>;
399 compatible = "arm,arm926ej-s";
405 // Example 4 (ARM Cortex-A57 64-bit system):
408 #address-cells = <2>;
412 compatible = "arm,cortex-a57";
414 enable-method = "spin-table";
415 cpu-release-addr = <0 0x20000000>;
420 compatible = "arm,cortex-a57";
422 enable-method = "spin-table";
423 cpu-release-addr = <0 0x20000000>;
428 compatible = "arm,cortex-a57";
430 enable-method = "spin-table";
431 cpu-release-addr = <0 0x20000000>;
436 compatible = "arm,cortex-a57";
438 enable-method = "spin-table";
439 cpu-release-addr = <0 0x20000000>;
444 compatible = "arm,cortex-a57";
446 enable-method = "spin-table";
447 cpu-release-addr = <0 0x20000000>;
452 compatible = "arm,cortex-a57";
454 enable-method = "spin-table";
455 cpu-release-addr = <0 0x20000000>;
460 compatible = "arm,cortex-a57";
462 enable-method = "spin-table";
463 cpu-release-addr = <0 0x20000000>;
468 compatible = "arm,cortex-a57";
470 enable-method = "spin-table";
471 cpu-release-addr = <0 0x20000000>;
476 compatible = "arm,cortex-a57";
478 enable-method = "spin-table";
479 cpu-release-addr = <0 0x20000000>;
484 compatible = "arm,cortex-a57";
486 enable-method = "spin-table";
487 cpu-release-addr = <0 0x20000000>;
492 compatible = "arm,cortex-a57";
494 enable-method = "spin-table";
495 cpu-release-addr = <0 0x20000000>;
500 compatible = "arm,cortex-a57";
502 enable-method = "spin-table";
503 cpu-release-addr = <0 0x20000000>;
508 compatible = "arm,cortex-a57";
510 enable-method = "spin-table";
511 cpu-release-addr = <0 0x20000000>;
516 compatible = "arm,cortex-a57";
518 enable-method = "spin-table";
519 cpu-release-addr = <0 0x20000000>;
524 compatible = "arm,cortex-a57";
526 enable-method = "spin-table";
527 cpu-release-addr = <0 0x20000000>;
532 compatible = "arm,cortex-a57";
534 enable-method = "spin-table";
535 cpu-release-addr = <0 0x20000000>;