1 # SPDX-License-Identifier: GPL-2.0
4 $id: http://devicetree.org/schemas/arm/cpus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM CPUs bindings
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
13 The device tree allows to describe the layout of CPUs in a system through
14 the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
15 defining properties for every cpu.
17 Bindings for CPU nodes follow the Devicetree Specification, available from:
19 https://www.devicetree.org/specifications/
21 with updates for 32-bit and 64-bit ARM systems provided in this document.
23 ================================
24 Convention used in this document
25 ================================
27 This document follows the conventions described in the Devicetree
28 Specification, with the addition:
30 - square brackets define bitfields, eg reg[7:0] value of the bitfield in
31 the reg property contained in bits 7 down to 0
33 =====================================
34 cpus and cpu node bindings definition
35 =====================================
37 The ARM architecture, in accordance with the Devicetree Specification,
38 requires the cpus and cpu nodes to be present and contain the properties
45 Usage and definition depend on ARM architecture version and
48 On uniprocessor ARM architectures previous to v7
49 this property is required and must be set to 0.
51 On ARM 11 MPcore based systems this property is
52 required and matches the CPUID[11:0] register bits.
54 Bits [11:0] in the reg cell must be set to
55 bits [11:0] in CPU ID register.
57 All other bits in the reg cell must be set to 0.
59 On 32-bit ARM v7 or later systems this property is
60 required and matches the CPU MPIDR[23:0] register
63 Bits [23:0] in the reg cell must be set to
66 All other bits in the reg cell must be set to 0.
68 On ARM v8 64-bit systems this property is required
69 and matches the MPIDR_EL1 register affinity bits.
71 * If cpus node's #address-cells property is set to 2
73 The first reg cell bits [7:0] must be set to
74 bits [39:32] of MPIDR_EL1.
76 The second reg cell bits [23:0] must be set to
77 bits [23:0] of MPIDR_EL1.
79 * If cpus node's #address-cells property is set to 1
81 The reg cell bits [23:0] must be set to bits [23:0]
84 All other bits in the reg cells must be set to 0.
118 - arm,armv8 # Only for s/w models
162 - nvidia,tegra132-denver
163 - nvidia,tegra186-denver
164 - nvidia,tegra194-carmel
175 $ref: '/schemas/types.yaml#/definitions/string'
177 # On ARM v8 64-bit this property is required
181 # On ARM 32-bit systems this property is optional
184 - allwinner,sun6i-a31
185 - allwinner,sun8i-a23
186 - allwinner,sun9i-a80-smp
187 - allwinner,sun8i-a83t-smp
189 - amlogic,meson8b-smp
192 - brcm,bcm11351-cpu-method
198 - marvell,armada-375-smp
199 - marvell,armada-380-smp
200 - marvell,armada-390-smp
201 - marvell,armada-xp-smp
202 - marvell,98dx3236-smp
204 - mediatek,mt6589-smp
205 - mediatek,mt81xx-tz-smp
210 - renesas,r9a06g032-smp
211 - rockchip,rk3036-smp
212 - rockchip,rk3066-smp
213 - socionext,milbeaut-m10v-smp
219 $ref: '/schemas/types.yaml#/definitions/uint64'
222 Required for systems that have an "enable-method"
223 property value of "spin-table".
224 On ARM v8 64-bit systems must be a two cell
225 property identifying a 64-bit zero-initialised
229 $ref: '/schemas/types.yaml#/definitions/phandle-array'
231 List of phandles to idle state nodes supported
232 by this cpu (see ./idle-states.yaml).
235 $ref: '/schemas/types.yaml#/definitions/uint32'
237 u32 value representing CPU capacity (see ./cpu-capacity.txt) in
238 DMIPS/MHz, relative to highest capacity-dmips-mhz
241 dynamic-power-coefficient:
242 $ref: '/schemas/types.yaml#/definitions/uint32'
244 A u32 value that represents the running time dynamic
245 power coefficient in units of uW/MHz/V^2. The
246 coefficient can either be calculated from power
247 measurements or derived by analysis.
249 The dynamic power consumption of the CPU is
250 proportional to the square of the Voltage (V) and
251 the clock frequency (f). The coefficient is used to
252 calculate the dynamic power as below -
254 Pdyn = dynamic-power-coefficient * V^2 * f
256 where voltage is in V, frequency is in MHz.
259 $ref: '/schemas/types.yaml#/definitions/phandle-array'
261 List of phandles and PM domain specifiers, as defined by bindings of the
262 PM domain provider (see also ../power_domain.txt).
265 $ref: '/schemas/types.yaml#/definitions/string-array'
267 A list of power domain name strings sorted in the same order as the
268 power-domains property.
270 For PSCI based platforms, the name corresponding to the index of the PSCI
271 PM domain provider, must be "psci".
274 $ref: '/schemas/types.yaml#/definitions/phandle'
276 Specifies the SAW* node associated with this CPU.
278 Required for systems that have an "enable-method" property
279 value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2"
281 * arm/msm/qcom,saw2.txt
284 $ref: '/schemas/types.yaml#/definitions/phandle'
286 Specifies the ACC* node associated with this CPU.
288 Required for systems that have an "enable-method" property
289 value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2"
291 * arm/msm/qcom,kpss-acc.txt
294 $ref: '/schemas/types.yaml#/definitions/phandle'
296 Specifies the syscon node controlling the cpu core power domains.
298 Optional for systems that have an "enable-method"
299 property value of "rockchip,rk3066-smp"
300 While optional, it is the preferred way to get access to
301 the cpu-core power-domains.
304 $ref: '/schemas/types.yaml#/definitions/uint32'
306 Required for systems that have an "enable-method" property value of
307 "brcm,bcm11351-cpu-method", "brcm,bcm23550" or "brcm,bcm-nsp-smp".
309 This includes the following SoCs: |
310 BCM11130, BCM11140, BCM11351, BCM28145, BCM28155, BCM21664, BCM23550
311 BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312
313 The secondary-boot-reg property is a u32 value that specifies the
314 physical address of the register used to request the ROM holding pen
315 code release a secondary CPU. The value written to the register is
316 formed by encoding the target CPU id into the low bits of the
317 physical start address it should jump to.
320 # If the enable-method property contains one of those values
325 - brcm,bcm11351-cpu-method
328 # and if enable-method is present
342 rockchip,pmu: [enable-method]
348 #address-cells = <1>;
352 compatible = "arm,cortex-a15";
358 compatible = "arm,cortex-a15";
364 compatible = "arm,cortex-a7";
370 compatible = "arm,cortex-a7";
376 // Example 2 (Cortex-A8 uniprocessor 32-bit system):
379 #address-cells = <1>;
383 compatible = "arm,cortex-a8";
389 // Example 3 (ARM 926EJ-S uniprocessor 32-bit system):
392 #address-cells = <1>;
396 compatible = "arm,arm926ej-s";
402 // Example 4 (ARM Cortex-A57 64-bit system):
405 #address-cells = <2>;
409 compatible = "arm,cortex-a57";
411 enable-method = "spin-table";
412 cpu-release-addr = <0 0x20000000>;
417 compatible = "arm,cortex-a57";
419 enable-method = "spin-table";
420 cpu-release-addr = <0 0x20000000>;
425 compatible = "arm,cortex-a57";
427 enable-method = "spin-table";
428 cpu-release-addr = <0 0x20000000>;
433 compatible = "arm,cortex-a57";
435 enable-method = "spin-table";
436 cpu-release-addr = <0 0x20000000>;
441 compatible = "arm,cortex-a57";
443 enable-method = "spin-table";
444 cpu-release-addr = <0 0x20000000>;
449 compatible = "arm,cortex-a57";
451 enable-method = "spin-table";
452 cpu-release-addr = <0 0x20000000>;
457 compatible = "arm,cortex-a57";
459 enable-method = "spin-table";
460 cpu-release-addr = <0 0x20000000>;
465 compatible = "arm,cortex-a57";
467 enable-method = "spin-table";
468 cpu-release-addr = <0 0x20000000>;
473 compatible = "arm,cortex-a57";
475 enable-method = "spin-table";
476 cpu-release-addr = <0 0x20000000>;
481 compatible = "arm,cortex-a57";
483 enable-method = "spin-table";
484 cpu-release-addr = <0 0x20000000>;
489 compatible = "arm,cortex-a57";
491 enable-method = "spin-table";
492 cpu-release-addr = <0 0x20000000>;
497 compatible = "arm,cortex-a57";
499 enable-method = "spin-table";
500 cpu-release-addr = <0 0x20000000>;
505 compatible = "arm,cortex-a57";
507 enable-method = "spin-table";
508 cpu-release-addr = <0 0x20000000>;
513 compatible = "arm,cortex-a57";
515 enable-method = "spin-table";
516 cpu-release-addr = <0 0x20000000>;
521 compatible = "arm,cortex-a57";
523 enable-method = "spin-table";
524 cpu-release-addr = <0 0x20000000>;
529 compatible = "arm,cortex-a57";
531 enable-method = "spin-table";
532 cpu-release-addr = <0 0x20000000>;