Documentation/devicetree/bindings/arm/cpus.txt

   1 =================
   2 ARM CPUs bindings
   3 =================
   4
   5 The device tree allows to describe the layout of CPUs in a system through
   6 the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
   7 defining properties for every cpu.
   8
   9 Bindings for CPU nodes follow the ePAPR v1.1 standard, available from:
  10
  11 https://www.power.org/documentation/epapr-version-1-1/
  12
  13 with updates for 32-bit and 64-bit ARM systems provided in this document.
  14
  15 ================================
  16 Convention used in this document
  17 ================================
  18
  19 This document follows the conventions described in the ePAPR v1.1, with
  20 the addition:
  21
  22 - square brackets define bitfields, eg reg[7:0] value of the bitfield in
  23   the reg property contained in bits 7 down to 0
  24
  25 =====================================
  26 cpus and cpu node bindings definition
  27 =====================================
  28
  29 The ARM architecture, in accordance with the ePAPR, requires the cpus and cpu
  30 nodes to be present and contain the properties described below.
  31
  32 - cpus node
  33
  34         Description: Container of cpu nodes
  35
  36         The node name must be "cpus".
  37
  38         A cpus node must define the following properties:
  39
  40         - #address-cells
  41                 Usage: required
  42                 Value type: <u32>
  43
  44                 Definition depends on ARM architecture version and
  45                 configuration:
  46
  47                         # On uniprocessor ARM architectures previous to v7
  48                           value must be 1, to enable a simple enumeration
  49                           scheme for processors that do not have a HW CPU
  50                           identification register.
  51                         # On 32-bit ARM 11 MPcore, ARM v7 or later systems
  52                           value must be 1, that corresponds to CPUID/MPIDR
  53                           registers sizes.
  54                         # On ARM v8 64-bit systems value should be set to 2,
  55                           that corresponds to the MPIDR_EL1 register size.
  56                           If MPIDR_EL1[63:32] value is equal to 0 on all CPUs
  57                           in the system, #address-cells can be set to 1, since
  58                           MPIDR_EL1[63:32] bits are not used for CPUs
  59                           identification.
  60         - #size-cells
  61                 Usage: required
  62                 Value type: <u32>
  63                 Definition: must be set to 0
  64
  65 - cpu node
  66
  67         Description: Describes a CPU in an ARM based system
  68
  69         PROPERTIES
  70
  71         - device_type
  72                 Usage: required
  73                 Value type: <string>
  74                 Definition: must be "cpu"
  75         - reg
  76                 Usage and definition depend on ARM architecture version and
  77                 configuration:
  78
  79                         # On uniprocessor ARM architectures previous to v7
  80                           this property is required and must be set to 0.
  81
  82                         # On ARM 11 MPcore based systems this property is
  83                           required and matches the CPUID[11:0] register bits.
  84
  85                           Bits [11:0] in the reg cell must be set to
  86                           bits [11:0] in CPU ID register.
  87
  88                           All other bits in the reg cell must be set to 0.
  89
  90                         # On 32-bit ARM v7 or later systems this property is
  91                           required and matches the CPU MPIDR[23:0] register
  92                           bits.
  93
  94                           Bits [23:0] in the reg cell must be set to
  95                           bits [23:0] in MPIDR.
  96
  97                           All other bits in the reg cell must be set to 0.
  98
  99                         # On ARM v8 64-bit systems this property is required
 100                           and matches the MPIDR_EL1 register affinity bits.
 101
 102                           * If cpus node's #address-cells property is set to 2
 103
 104                             The first reg cell bits [7:0] must be set to
 105                             bits [39:32] of MPIDR_EL1.
 106
 107                             The second reg cell bits [23:0] must be set to
 108                             bits [23:0] of MPIDR_EL1.
 109
 110                           * If cpus node's #address-cells property is set to 1
 111
 112                             The reg cell bits [23:0] must be set to bits [23:0]
 113                             of MPIDR_EL1.
 114
 115                           All other bits in the reg cells must be set to 0.
 116
 117         - compatible:
 118                 Usage: required
 119                 Value type: <string>
 120                 Definition: should be one of:
 121                             "arm,arm710t"
 122                             "arm,arm720t"
 123                             "arm,arm740t"
 124                             "arm,arm7ej-s"
 125                             "arm,arm7tdmi"
 126                             "arm,arm7tdmi-s"
 127                             "arm,arm9es"
 128                             "arm,arm9ej-s"
 129                             "arm,arm920t"
 130                             "arm,arm922t"
 131                             "arm,arm925"
 132                             "arm,arm926e-s"
 133                             "arm,arm926ej-s"
 134                             "arm,arm940t"
 135                             "arm,arm946e-s"
 136                             "arm,arm966e-s"
 137                             "arm,arm968e-s"
 138                             "arm,arm9tdmi"
 139                             "arm,arm1020e"
 140                             "arm,arm1020t"
 141                             "arm,arm1022e"
 142                             "arm,arm1026ej-s"
 143                             "arm,arm1136j-s"
 144                             "arm,arm1136jf-s"
 145                             "arm,arm1156t2-s"
 146                             "arm,arm1156t2f-s"
 147                             "arm,arm1176jzf"
 148                             "arm,arm1176jz-s"
 149                             "arm,arm1176jzf-s"
 150                             "arm,arm11mpcore"
 151                             "arm,cortex-a5"
 152                             "arm,cortex-a7"
 153                             "arm,cortex-a8"
 154                             "arm,cortex-a9"
 155                             "arm,cortex-a12"
 156                             "arm,cortex-a15"
 157                             "arm,cortex-a17"
 158                             "arm,cortex-a53"
 159                             "arm,cortex-a57"
 160                             "arm,cortex-a72"
 161                             "arm,cortex-m0"
 162                             "arm,cortex-m0+"
 163                             "arm,cortex-m1"
 164                             "arm,cortex-m3"
 165                             "arm,cortex-m4"
 166                             "arm,cortex-r4"
 167                             "arm,cortex-r5"
 168                             "arm,cortex-r7"
 169                             "brcm,brahma-b15"
 170                             "brcm,vulcan"
 171                             "cavium,thunder"
 172                             "faraday,fa526"
 173                             "intel,sa110"
 174                             "intel,sa1100"
 175                             "marvell,feroceon"
 176                             "marvell,mohawk"
 177                             "marvell,pj4a"
 178                             "marvell,pj4b"
 179                             "marvell,sheeva-v5"
 180                             "nvidia,tegra132-denver"
 181                             "qcom,krait"
 182                             "qcom,kryo"
 183                             "qcom,scorpion"
 184         - enable-method
 185                 Value type: <stringlist>
 186                 Usage and definition depend on ARM architecture version.
 187                         # On ARM v8 64-bit this property is required and must
 188                           be one of:
 189                              "psci"
 190                              "spin-table"
 191                         # On ARM 32-bit systems this property is optional and
 192                           can be one of:
 193                             "allwinner,sun6i-a31"
 194                             "allwinner,sun8i-a23"
 195                             "arm,realview-smp"
 196                             "brcm,bcm11351-cpu-method"
 197                             "brcm,bcm23550"
 198                             "brcm,bcm-nsp-smp"
 199                             "brcm,brahma-b15"
 200                             "marvell,armada-375-smp"
 201                             "marvell,armada-380-smp"
 202                             "marvell,armada-390-smp"
 203                             "marvell,armada-xp-smp"
 204                             "mediatek,mt6589-smp"
 205                             "mediatek,mt81xx-tz-smp"
 206                             "qcom,gcc-msm8660"
 207                             "qcom,kpss-acc-v1"
 208                             "qcom,kpss-acc-v2"
 209                             "rockchip,rk3036-smp"
 210                             "rockchip,rk3066-smp"
 211                             "ste,dbx500-smp"
 212
 213         - cpu-release-addr
 214                 Usage: required for systems that have an "enable-method"
 215                        property value of "spin-table".
 216                 Value type: <prop-encoded-array>
 217                 Definition:
 218                         # On ARM v8 64-bit systems must be a two cell
 219                           property identifying a 64-bit zero-initialised
 220                           memory location.
 221
 222         - qcom,saw
 223                 Usage: required for systems that have an "enable-method"
 224                        property value of "qcom,kpss-acc-v1" or
 225                        "qcom,kpss-acc-v2"
 226                 Value type: <phandle>
 227                 Definition: Specifies the SAW[1] node associated with this CPU.
 228
 229         - qcom,acc
 230                 Usage: required for systems that have an "enable-method"
 231                        property value of "qcom,kpss-acc-v1" or
 232                        "qcom,kpss-acc-v2"
 233                 Value type: <phandle>
 234                 Definition: Specifies the ACC[2] node associated with this CPU.
 235
 236         - cpu-idle-states
 237                 Usage: Optional
 238                 Value type: <prop-encoded-array>
 239                 Definition:
 240                         # List of phandles to idle state nodes supported
 241                           by this cpu [3].
 242
 243         - rockchip,pmu
 244                 Usage: optional for systems that have an "enable-method"
 245                        property value of "rockchip,rk3066-smp"
 246                        While optional, it is the preferred way to get access to
 247                        the cpu-core power-domains.
 248                 Value type: <phandle>
 249                 Definition: Specifies the syscon node controlling the cpu core
 250                             power domains.
 251
 252         - dynamic-power-coefficient
 253                 Usage: optional
 254                 Value type: <prop-encoded-array>
 255                 Definition: A u32 value that represents the running time dynamic
 256                             power coefficient in units of mW/MHz/uV^2. The
 257                             coefficient can either be calculated from power
 258                             measurements or derived by analysis.
 259
 260                             The dynamic power consumption of the CPU  is
 261                             proportional to the square of the Voltage (V) and
 262                             the clock frequency (f). The coefficient is used to
 263                             calculate the dynamic power as below -
 264
 265                             Pdyn = dynamic-power-coefficient * V^2 * f
 266
 267                             where voltage is in uV, frequency is in MHz.
 268
 269 Example 1 (dual-cluster big.LITTLE system 32-bit):
 270
 271         cpus {
 272                 #size-cells = <0>;
 273                 #address-cells = <1>;
 274
 275                 cpu@0 {
 276                         device_type = "cpu";
 277                         compatible = "arm,cortex-a15";
 278                         reg = <0x0>;
 279                 };
 280
 281                 cpu@1 {
 282                         device_type = "cpu";
 283                         compatible = "arm,cortex-a15";
 284                         reg = <0x1>;
 285                 };
 286
 287                 cpu@100 {
 288                         device_type = "cpu";
 289                         compatible = "arm,cortex-a7";
 290                         reg = <0x100>;
 291                 };
 292
 293                 cpu@101 {
 294                         device_type = "cpu";
 295                         compatible = "arm,cortex-a7";
 296                         reg = <0x101>;
 297                 };
 298         };
 299
 300 Example 2 (Cortex-A8 uniprocessor 32-bit system):
 301
 302         cpus {
 303                 #size-cells = <0>;
 304                 #address-cells = <1>;
 305
 306                 cpu@0 {
 307                         device_type = "cpu";
 308                         compatible = "arm,cortex-a8";
 309                         reg = <0x0>;
 310                 };
 311         };
 312
 313 Example 3 (ARM 926EJ-S uniprocessor 32-bit system):
 314
 315         cpus {
 316                 #size-cells = <0>;
 317                 #address-cells = <1>;
 318
 319                 cpu@0 {
 320                         device_type = "cpu";
 321                         compatible = "arm,arm926ej-s";
 322                         reg = <0x0>;
 323                 };
 324         };
 325
 326 Example 4 (ARM Cortex-A57 64-bit system):
 327
 328 cpus {
 329         #size-cells = <0>;
 330         #address-cells = <2>;
 331
 332         cpu@0 {
 333                 device_type = "cpu";
 334                 compatible = "arm,cortex-a57";
 335                 reg = <0x0 0x0>;
 336                 enable-method = "spin-table";
 337                 cpu-release-addr = <0 0x20000000>;
 338         };
 339
 340         cpu@1 {
 341                 device_type = "cpu";
 342                 compatible = "arm,cortex-a57";
 343                 reg = <0x0 0x1>;
 344                 enable-method = "spin-table";
 345                 cpu-release-addr = <0 0x20000000>;
 346         };
 347
 348         cpu@100 {
 349                 device_type = "cpu";
 350                 compatible = "arm,cortex-a57";
 351                 reg = <0x0 0x100>;
 352                 enable-method = "spin-table";
 353                 cpu-release-addr = <0 0x20000000>;
 354         };
 355
 356         cpu@101 {
 357                 device_type = "cpu";
 358                 compatible = "arm,cortex-a57";
 359                 reg = <0x0 0x101>;
 360                 enable-method = "spin-table";
 361                 cpu-release-addr = <0 0x20000000>;
 362         };
 363
 364         cpu@10000 {
 365                 device_type = "cpu";
 366                 compatible = "arm,cortex-a57";
 367                 reg = <0x0 0x10000>;
 368                 enable-method = "spin-table";
 369                 cpu-release-addr = <0 0x20000000>;
 370         };
 371
 372         cpu@10001 {
 373                 device_type = "cpu";
 374                 compatible = "arm,cortex-a57";
 375                 reg = <0x0 0x10001>;
 376                 enable-method = "spin-table";
 377                 cpu-release-addr = <0 0x20000000>;
 378         };
 379
 380         cpu@10100 {
 381                 device_type = "cpu";
 382                 compatible = "arm,cortex-a57";
 383                 reg = <0x0 0x10100>;
 384                 enable-method = "spin-table";
 385                 cpu-release-addr = <0 0x20000000>;
 386         };
 387
 388         cpu@10101 {
 389                 device_type = "cpu";
 390                 compatible = "arm,cortex-a57";
 391                 reg = <0x0 0x10101>;
 392                 enable-method = "spin-table";
 393                 cpu-release-addr = <0 0x20000000>;
 394         };
 395
 396         cpu@100000000 {
 397                 device_type = "cpu";
 398                 compatible = "arm,cortex-a57";
 399                 reg = <0x1 0x0>;
 400                 enable-method = "spin-table";
 401                 cpu-release-addr = <0 0x20000000>;
 402         };
 403
 404         cpu@100000001 {
 405                 device_type = "cpu";
 406                 compatible = "arm,cortex-a57";
 407                 reg = <0x1 0x1>;
 408                 enable-method = "spin-table";
 409                 cpu-release-addr = <0 0x20000000>;
 410         };
 411
 412         cpu@100000100 {
 413                 device_type = "cpu";
 414                 compatible = "arm,cortex-a57";
 415                 reg = <0x1 0x100>;
 416                 enable-method = "spin-table";
 417                 cpu-release-addr = <0 0x20000000>;
 418         };
 419
 420         cpu@100000101 {
 421                 device_type = "cpu";
 422                 compatible = "arm,cortex-a57";
 423                 reg = <0x1 0x101>;
 424                 enable-method = "spin-table";
 425                 cpu-release-addr = <0 0x20000000>;
 426         };
 427
 428         cpu@100010000 {
 429                 device_type = "cpu";
 430                 compatible = "arm,cortex-a57";
 431                 reg = <0x1 0x10000>;
 432                 enable-method = "spin-table";
 433                 cpu-release-addr = <0 0x20000000>;
 434         };
 435
 436         cpu@100010001 {
 437                 device_type = "cpu";
 438                 compatible = "arm,cortex-a57";
 439                 reg = <0x1 0x10001>;
 440                 enable-method = "spin-table";
 441                 cpu-release-addr = <0 0x20000000>;
 442         };
 443
 444         cpu@100010100 {
 445                 device_type = "cpu";
 446                 compatible = "arm,cortex-a57";
 447                 reg = <0x1 0x10100>;
 448                 enable-method = "spin-table";
 449                 cpu-release-addr = <0 0x20000000>;
 450         };
 451
 452         cpu@100010101 {
 453                 device_type = "cpu";
 454                 compatible = "arm,cortex-a57";
 455                 reg = <0x1 0x10101>;
 456                 enable-method = "spin-table";
 457                 cpu-release-addr = <0 0x20000000>;
 458         };
 459 };
 460
 461 --
 462 [1] arm/msm/qcom,saw2.txt
 463 [2] arm/msm/qcom,kpss-acc.txt
 464 [3] ARM Linux kernel documentation - idle states bindings
 465     Documentation/devicetree/bindings/arm/idle-states.txt