5 The device tree allows to describe the layout of CPUs in a system through
6 the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
7 defining properties for every cpu.
9 Bindings for CPU nodes follow the Devicetree Specification, available from:
11 https://www.devicetree.org/specifications/
13 with updates for 32-bit and 64-bit ARM systems provided in this document.
15 ================================
16 Convention used in this document
17 ================================
19 This document follows the conventions described in the Devicetree
20 Specification, with the addition:
22 - square brackets define bitfields, eg reg[7:0] value of the bitfield in
23 the reg property contained in bits 7 down to 0
25 =====================================
26 cpus and cpu node bindings definition
27 =====================================
29 The ARM architecture, in accordance with the Devicetree Specification,
30 requires the cpus and cpu nodes to be present and contain the properties
35 Description: Container of cpu nodes
37 The node name must be "cpus".
39 A cpus node must define the following properties:
45 Definition depends on ARM architecture version and
48 # On uniprocessor ARM architectures previous to v7
49 value must be 1, to enable a simple enumeration
50 scheme for processors that do not have a HW CPU
51 identification register.
52 # On 32-bit ARM 11 MPcore, ARM v7 or later systems
53 value must be 1, that corresponds to CPUID/MPIDR
55 # On ARM v8 64-bit systems value should be set to 2,
56 that corresponds to the MPIDR_EL1 register size.
57 If MPIDR_EL1[63:32] value is equal to 0 on all CPUs
58 in the system, #address-cells can be set to 1, since
59 MPIDR_EL1[63:32] bits are not used for CPUs
64 Definition: must be set to 0
68 Description: Describes a CPU in an ARM based system
75 Definition: must be "cpu"
77 Usage and definition depend on ARM architecture version and
80 # On uniprocessor ARM architectures previous to v7
81 this property is required and must be set to 0.
83 # On ARM 11 MPcore based systems this property is
84 required and matches the CPUID[11:0] register bits.
86 Bits [11:0] in the reg cell must be set to
87 bits [11:0] in CPU ID register.
89 All other bits in the reg cell must be set to 0.
91 # On 32-bit ARM v7 or later systems this property is
92 required and matches the CPU MPIDR[23:0] register
95 Bits [23:0] in the reg cell must be set to
98 All other bits in the reg cell must be set to 0.
100 # On ARM v8 64-bit systems this property is required
101 and matches the MPIDR_EL1 register affinity bits.
103 * If cpus node's #address-cells property is set to 2
105 The first reg cell bits [7:0] must be set to
106 bits [39:32] of MPIDR_EL1.
108 The second reg cell bits [23:0] must be set to
109 bits [23:0] of MPIDR_EL1.
111 * If cpus node's #address-cells property is set to 1
113 The reg cell bits [23:0] must be set to bits [23:0]
116 All other bits in the reg cells must be set to 0.
121 Definition: should be one of:
184 "nvidia,tegra132-denver"
185 "nvidia,tegra186-denver"
191 Value type: <stringlist>
192 Usage and definition depend on ARM architecture version.
193 # On ARM v8 64-bit this property is required and must
197 # On ARM 32-bit systems this property is optional and
200 "allwinner,sun6i-a31"
201 "allwinner,sun8i-a23"
202 "allwinner,sun9i-a80-smp"
204 "amlogic,meson8b-smp"
206 "brcm,bcm11351-cpu-method"
211 "marvell,armada-375-smp"
212 "marvell,armada-380-smp"
213 "marvell,armada-390-smp"
214 "marvell,armada-xp-smp"
215 "marvell,98dx3236-smp"
216 "mediatek,mt6589-smp"
217 "mediatek,mt81xx-tz-smp"
222 "rockchip,rk3036-smp"
223 "rockchip,rk3066-smp"
227 Usage: required for systems that have an "enable-method"
228 property value of "spin-table".
229 Value type: <prop-encoded-array>
231 # On ARM v8 64-bit systems must be a two cell
232 property identifying a 64-bit zero-initialised
236 Usage: required for systems that have an "enable-method"
237 property value of "qcom,kpss-acc-v1" or
239 Value type: <phandle>
240 Definition: Specifies the SAW[1] node associated with this CPU.
243 Usage: required for systems that have an "enable-method"
244 property value of "qcom,kpss-acc-v1" or
246 Value type: <phandle>
247 Definition: Specifies the ACC[2] node associated with this CPU.
251 Value type: <prop-encoded-array>
253 # List of phandles to idle state nodes supported
260 # u32 value representing CPU capacity [4] in
261 DMIPS/MHz, relative to highest capacity-dmips-mhz
265 Usage: optional for systems that have an "enable-method"
266 property value of "rockchip,rk3066-smp"
267 While optional, it is the preferred way to get access to
268 the cpu-core power-domains.
269 Value type: <phandle>
270 Definition: Specifies the syscon node controlling the cpu core
273 - dynamic-power-coefficient
275 Value type: <prop-encoded-array>
276 Definition: A u32 value that represents the running time dynamic
277 power coefficient in units of mW/MHz/uV^2. The
278 coefficient can either be calculated from power
279 measurements or derived by analysis.
281 The dynamic power consumption of the CPU is
282 proportional to the square of the Voltage (V) and
283 the clock frequency (f). The coefficient is used to
284 calculate the dynamic power as below -
286 Pdyn = dynamic-power-coefficient * V^2 * f
288 where voltage is in uV, frequency is in MHz.
290 Example 1 (dual-cluster big.LITTLE system 32-bit):
294 #address-cells = <1>;
298 compatible = "arm,cortex-a15";
304 compatible = "arm,cortex-a15";
310 compatible = "arm,cortex-a7";
316 compatible = "arm,cortex-a7";
321 Example 2 (Cortex-A8 uniprocessor 32-bit system):
325 #address-cells = <1>;
329 compatible = "arm,cortex-a8";
334 Example 3 (ARM 926EJ-S uniprocessor 32-bit system):
338 #address-cells = <1>;
342 compatible = "arm,arm926ej-s";
347 Example 4 (ARM Cortex-A57 64-bit system):
351 #address-cells = <2>;
355 compatible = "arm,cortex-a57";
357 enable-method = "spin-table";
358 cpu-release-addr = <0 0x20000000>;
363 compatible = "arm,cortex-a57";
365 enable-method = "spin-table";
366 cpu-release-addr = <0 0x20000000>;
371 compatible = "arm,cortex-a57";
373 enable-method = "spin-table";
374 cpu-release-addr = <0 0x20000000>;
379 compatible = "arm,cortex-a57";
381 enable-method = "spin-table";
382 cpu-release-addr = <0 0x20000000>;
387 compatible = "arm,cortex-a57";
389 enable-method = "spin-table";
390 cpu-release-addr = <0 0x20000000>;
395 compatible = "arm,cortex-a57";
397 enable-method = "spin-table";
398 cpu-release-addr = <0 0x20000000>;
403 compatible = "arm,cortex-a57";
405 enable-method = "spin-table";
406 cpu-release-addr = <0 0x20000000>;
411 compatible = "arm,cortex-a57";
413 enable-method = "spin-table";
414 cpu-release-addr = <0 0x20000000>;
419 compatible = "arm,cortex-a57";
421 enable-method = "spin-table";
422 cpu-release-addr = <0 0x20000000>;
427 compatible = "arm,cortex-a57";
429 enable-method = "spin-table";
430 cpu-release-addr = <0 0x20000000>;
435 compatible = "arm,cortex-a57";
437 enable-method = "spin-table";
438 cpu-release-addr = <0 0x20000000>;
443 compatible = "arm,cortex-a57";
445 enable-method = "spin-table";
446 cpu-release-addr = <0 0x20000000>;
451 compatible = "arm,cortex-a57";
453 enable-method = "spin-table";
454 cpu-release-addr = <0 0x20000000>;
459 compatible = "arm,cortex-a57";
461 enable-method = "spin-table";
462 cpu-release-addr = <0 0x20000000>;
467 compatible = "arm,cortex-a57";
469 enable-method = "spin-table";
470 cpu-release-addr = <0 0x20000000>;
475 compatible = "arm,cortex-a57";
477 enable-method = "spin-table";
478 cpu-release-addr = <0 0x20000000>;
483 [1] arm/msm/qcom,saw2.txt
484 [2] arm/msm/qcom,kpss-acc.txt
485 [3] ARM Linux kernel documentation - idle states bindings
486 Documentation/devicetree/bindings/arm/idle-states.txt
487 [4] ARM Linux kernel documentation - cpu capacity bindings
488 Documentation/devicetree/bindings/arm/cpu-capacity.txt