1 * CoreSight Components:
3 CoreSight components are compliant with the ARM CoreSight architecture
4 specification and can be connected in various topologies to suit a particular
5 SoCs tracing needs. These trace components can generally be classified as
6 sinks, links and sources. Trace data produced by one or more sources flows
7 through the intermediate links connecting the source to the currently selected
8 sink. Each CoreSight component device should use these properties to describe
9 its hardware characteristcs.
11 * Required properties for all components *except* non-configurable replicators
12 and non-configurable funnels:
14 * compatible: These have to be supplemented with "arm,primecell" as
15 drivers are using the AMBA bus interface. Possible values include:
16 - Embedded Trace Buffer (version 1.0):
17 "arm,coresight-etb10", "arm,primecell";
19 - Trace Port Interface Unit:
20 "arm,coresight-tpiu", "arm,primecell";
22 - Trace Memory Controller, used for Embedded Trace Buffer(ETB),
23 Embedded Trace FIFO(ETF) and Embedded Trace Router(ETR)
24 configuration. The configuration mode (ETB, ETF, ETR) is
25 discovered at boot time when the device is probed.
26 "arm,coresight-tmc", "arm,primecell";
28 - Trace Programmable Funnel:
29 "arm,coresight-dynamic-funnel", "arm,primecell";
30 "arm,coresight-funnel", "arm,primecell"; (OBSOLETE. For
31 backward compatibility and will be removed)
33 - Embedded Trace Macrocell (version 3.x) and
34 Program Flow Trace Macrocell:
35 "arm,coresight-etm3x", "arm,primecell";
37 - Embedded Trace Macrocell (version 4.x), with memory mapped access.
38 "arm,coresight-etm4x", "arm,primecell";
40 - Embedded Trace Macrocell (version 4.x), with system register access only.
41 "arm,coresight-etm4x-sysreg";
43 - Coresight programmable Replicator :
44 "arm,coresight-dynamic-replicator", "arm,primecell";
46 - System Trace Macrocell:
47 "arm,coresight-stm", "arm,primecell"; [1]
48 - Coresight Address Translation Unit (CATU)
49 "arm,coresight-catu", "arm,primecell";
51 - Coresight Cross Trigger Interface (CTI):
52 "arm,coresight-cti", "arm,primecell";
53 See coresight-cti.yaml for full CTI definitions.
55 * reg: physical base address and length of the register
56 set(s) of the component.
58 * clocks: the clocks associated to this component.
60 * clock-names: the name of the clocks referenced by the code.
61 Since we are using the AMBA framework, the name of the clock
62 providing the interconnect should be "apb_pclk", and some
63 coresight blocks also have an additional clock "atclk", which
64 clocks the core of that coresight component. The latter clock
67 * port or ports: see "Graph bindings for Coresight" below.
69 * Additional required property for Embedded Trace Macrocell (version 3.x and
71 * cpu: the cpu phandle this ETM/PTM is affined to. Do not
72 assume it to default to CPU0 if omitted.
74 * Additional required properties for System Trace Macrocells (STM):
75 * reg: along with the physical base address and length of the register
76 set as described above, another entry is required to describe the
77 mapping of the extended stimulus port area.
79 * reg-names: the only acceptable values are "stm-base" and
80 "stm-stimulus-base", each corresponding to the areas defined in "reg".
82 * Required properties for Coresight Cross Trigger Interface (CTI)
83 See coresight-cti.yaml for full CTI definitions.
85 * Required properties for devices that don't show up on the AMBA bus, such as
86 non-configurable replicators and non-configurable funnels:
88 * compatible: Currently supported value is (note the absence of the
90 - Coresight Non-configurable Replicator:
91 "arm,coresight-static-replicator";
92 "arm,coresight-replicator"; (OBSOLETE. For backward
93 compatibility and will be removed)
95 - Coresight Non-configurable Funnel:
96 "arm,coresight-static-funnel";
98 * port or ports: see "Graph bindings for Coresight" below.
100 * Optional properties for all components:
102 * arm,coresight-loses-context-with-cpu : boolean. Indicates that the
103 hardware will lose register context on CPU power down (e.g. CPUIdle).
104 An example of where this may be needed are systems which contain a
105 coresight component and CPU in the same power domain. When the CPU
106 powers down the coresight component also powers down and loses its
107 context. This property is currently only used for the ETM 4.x driver.
109 * Optional properties for ETM/PTMs:
111 * arm,cp14: must be present if the system accesses ETM/PTM management
112 registers via co-processor 14.
114 * qcom,skip-power-up: boolean. Indicates that an implementation can
115 skip powering up the trace unit. TRCPDCR.PU does not have to be set
116 on Qualcomm Technologies Inc. systems since ETMs are in the same power
117 domain as their CPU cores. This property is required to identify such
118 systems with hardware errata where the CPU watchdog counter is stopped
119 when TRCPDCR.PU is set.
121 * Optional property for TMC:
123 * arm,buffer-size: size of contiguous buffer space for TMC ETR
124 (embedded trace router). This property is obsolete. The buffer size
125 can be configured dynamically via buffer_size property in sysfs.
127 * arm,scatter-gather: boolean. Indicates that the TMC-ETR can safely
128 use the SG mode on this system.
130 * Optional property for CATU :
131 * interrupts : Exactly one SPI may be listed for reporting the address
134 * Optional property for configurable replicators:
136 * qcom,replicator-loses-context: boolean. Indicates that the replicator
137 will lose register context when AMBA clock is removed which is observed
138 in some replicator designs.
140 Graph bindings for Coresight
141 -------------------------------
143 Coresight components are interconnected to create a data path for the flow of
144 trace data generated from the "sources" to their collection points "sink".
145 Each coresight component must describe the "input" and "output" connections.
146 The connections must be described via generic DT graph bindings as described
147 by the "bindings/graph.txt", where each "port" along with an "endpoint"
148 component represents a hardware port and the connection.
150 * All output ports must be listed inside a child node named "out-ports"
151 * All input ports must be listed inside a child node named "in-ports".
152 * Port address must match the hardware port number.
158 compatible = "arm,coresight-etb10", "arm,primecell";
159 reg = <0 0x20010000 0 0x1000>;
161 clocks = <&oscclk6a>;
162 clock-names = "apb_pclk";
165 etb_in_port: endpoint@0 {
166 remote-endpoint = <&replicator_out_port0>;
173 compatible = "arm,coresight-tpiu", "arm,primecell";
174 reg = <0 0x20030000 0 0x1000>;
176 clocks = <&oscclk6a>;
177 clock-names = "apb_pclk";
180 tpiu_in_port: endpoint@0 {
181 remote-endpoint = <&replicator_out_port1>;
188 compatible = "arm,coresight-tmc", "arm,primecell";
189 reg = <0 0x20070000 0 0x1000>;
191 clocks = <&oscclk6a>;
192 clock-names = "apb_pclk";
195 etr_in_port: endpoint {
196 remote-endpoint = <&replicator2_out_port0>;
203 etr_out_port: endpoint {
204 remote-endpoint = <&catu_in_port>;
212 /* non-configurable replicators don't show up on the
213 * AMBA bus. As such no need to add "arm,primecell".
215 compatible = "arm,coresight-static-replicator";
218 #address-cells = <1>;
221 /* replicator output ports */
224 replicator_out_port0: endpoint {
225 remote-endpoint = <&etb_in_port>;
231 replicator_out_port1: endpoint {
232 remote-endpoint = <&tpiu_in_port>;
239 replicator_in_port0: endpoint {
240 remote-endpoint = <&funnel_out_port0>;
248 * non-configurable funnel don't show up on the AMBA
249 * bus. As such no need to add "arm,primecell".
251 compatible = "arm,coresight-static-funnel";
252 clocks = <&crg_ctrl HI3660_PCLK>;
253 clock-names = "apb_pclk";
257 combo_funnel_out: endpoint {
258 remote-endpoint = <&top_funnel_in>;
264 #address-cells = <1>;
269 combo_funnel_in0: endpoint {
270 remote-endpoint = <&cluster0_etf_out>;
276 combo_funnel_in1: endpoint {
277 remote-endpoint = <&cluster1_etf_out>;
284 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
285 reg = <0 0x20040000 0 0x1000>;
287 clocks = <&oscclk6a>;
288 clock-names = "apb_pclk";
291 funnel_out_port0: endpoint {
293 <&replicator_in_port0>;
299 #address-cells = <1>;
304 funnel_in_port0: endpoint {
305 remote-endpoint = <&ptm0_out_port>;
311 funnel_in_port1: endpoint {
312 remote-endpoint = <&ptm1_out_port>;
318 funnel_in_port2: endpoint {
319 remote-endpoint = <&etm0_out_port>;
328 compatible = "arm,coresight-etm3x", "arm,primecell";
329 reg = <0 0x2201c000 0 0x1000>;
332 clocks = <&oscclk6a>;
333 clock-names = "apb_pclk";
336 ptm0_out_port: endpoint {
337 remote-endpoint = <&funnel_in_port0>;
344 compatible = "arm,coresight-etm3x", "arm,primecell";
345 reg = <0 0x2201d000 0 0x1000>;
348 clocks = <&oscclk6a>;
349 clock-names = "apb_pclk";
352 ptm1_out_port: endpoint {
353 remote-endpoint = <&funnel_in_port1>;
361 compatible = "arm,coresight-stm", "arm,primecell";
362 reg = <0 0x20100000 0 0x1000>,
363 <0 0x28000000 0 0x180000>;
364 reg-names = "stm-base", "stm-stimulus-base";
366 clocks = <&soc_smc50mhz>;
367 clock-names = "apb_pclk";
370 stm_out_port: endpoint {
371 remote-endpoint = <&main_funnel_in_port2>;
380 compatible = "arm,coresight-catu", "arm,primecell";
381 reg = <0 0x207e0000 0 0x1000>;
383 clocks = <&oscclk6a>;
384 clock-names = "apb_pclk";
386 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
389 catu_in_port: endpoint {
390 remote-endpoint = <&etr_out_port>;
396 [1]. There is currently two version of STM: STM32 and STM500. Both
397 have the same HW interface and as such don't need an explicit binding name.