Documentation/devicetree/bindings/arm/coresight.txt

   1 * CoreSight Components:
   2
   3 CoreSight components are compliant with the ARM CoreSight architecture
   4 specification and can be connected in various topologies to suit a particular
   5 SoCs tracing needs. These trace components can generally be classified as
   6 sinks, links and sources. Trace data produced by one or more sources flows
   7 through the intermediate links connecting the source to the currently selected
   8 sink. Each CoreSight component device should use these properties to describe
   9 its hardware characteristcs.
  10
  11 * Required properties for all components *except* non-configurable replicators
  12   and non-configurable funnels:
  13
  14         * compatible: These have to be supplemented with "arm,primecell" as
  15           drivers are using the AMBA bus interface.  Possible values include:
  16                 - Embedded Trace Buffer (version 1.0):
  17                         "arm,coresight-etb10", "arm,primecell";
  18
  19                 - Trace Port Interface Unit:
  20                         "arm,coresight-tpiu", "arm,primecell";
  21
  22                 - Trace Memory Controller, used for Embedded Trace Buffer(ETB),
  23                   Embedded Trace FIFO(ETF) and Embedded Trace Router(ETR)
  24                   configuration.  The configuration mode (ETB, ETF, ETR) is
  25                   discovered at boot time when the device is probed.
  26                         "arm,coresight-tmc", "arm,primecell";
  27
  28                 - Trace Programmable Funnel:
  29                         "arm,coresight-dynamic-funnel", "arm,primecell";
  30                         "arm,coresight-funnel", "arm,primecell"; (OBSOLETE. For
  31                                 backward compatibility and will be removed)
  32
  33                 - Embedded Trace Macrocell (version 3.x) and
  34                                         Program Flow Trace Macrocell:
  35                         "arm,coresight-etm3x", "arm,primecell";
  36
  37                 - Embedded Trace Macrocell (version 4.x), with memory mapped access.
  38                         "arm,coresight-etm4x", "arm,primecell";
  39
  40                 - Embedded Trace Macrocell (version 4.x), with system register access only.
  41                         "arm,coresight-etm4x-sysreg";
  42
  43                 - Coresight programmable Replicator :
  44                         "arm,coresight-dynamic-replicator", "arm,primecell";
  45
  46                 - System Trace Macrocell:
  47                         "arm,coresight-stm", "arm,primecell"; [1]
  48                 - Coresight Address Translation Unit (CATU)
  49                         "arm,coresight-catu", "arm,primecell";
  50
  51                 - Coresight Cross Trigger Interface (CTI):
  52                         "arm,coresight-cti", "arm,primecell";
  53                         See coresight-cti.yaml for full CTI definitions.
  54
  55         * reg: physical base address and length of the register
  56           set(s) of the component.
  57
  58         * clocks: the clocks associated to this component.
  59
  60         * clock-names: the name of the clocks referenced by the code.
  61           Since we are using the AMBA framework, the name of the clock
  62           providing the interconnect should be "apb_pclk", and some
  63           coresight blocks also have an additional clock "atclk", which
  64           clocks the core of that coresight component. The latter clock
  65           is optional.
  66
  67         * port or ports: see "Graph bindings for Coresight" below.
  68
  69 * Additional required property for Embedded Trace Macrocell (version 3.x and
  70   version 4.x):
  71         * cpu: the cpu phandle this ETM/PTM is affined to. Do not
  72           assume it to default to CPU0 if omitted.
  73
  74 * Additional required properties for System Trace Macrocells (STM):
  75         * reg: along with the physical base address and length of the register
  76           set as described above, another entry is required to describe the
  77           mapping of the extended stimulus port area.
  78
  79         * reg-names: the only acceptable values are "stm-base" and
  80           "stm-stimulus-base", each corresponding to the areas defined in "reg".
  81
  82 * Required properties for Coresight Cross Trigger Interface (CTI)
  83         See coresight-cti.yaml for full CTI definitions.
  84
  85 * Required properties for devices that don't show up on the AMBA bus, such as
  86   non-configurable replicators and non-configurable funnels:
  87
  88         * compatible: Currently supported value is (note the absence of the
  89           AMBA markee):
  90                 - Coresight Non-configurable Replicator:
  91                         "arm,coresight-static-replicator";
  92                         "arm,coresight-replicator"; (OBSOLETE. For backward
  93                                 compatibility and will be removed)
  94
  95                 - Coresight Non-configurable Funnel:
  96                         "arm,coresight-static-funnel";
  97
  98         * port or ports: see "Graph bindings for Coresight" below.
  99
 100 * Optional properties for all components:
 101
 102         * arm,coresight-loses-context-with-cpu : boolean. Indicates that the
 103           hardware will lose register context on CPU power down (e.g. CPUIdle).
 104           An example of where this may be needed are systems which contain a
 105           coresight component and CPU in the same power domain. When the CPU
 106           powers down the coresight component also powers down and loses its
 107           context. This property is currently only used for the ETM 4.x driver.
 108
 109 * Optional properties for ETM/PTMs:
 110
 111         * arm,cp14: must be present if the system accesses ETM/PTM management
 112           registers via co-processor 14.
 113
 114         * qcom,skip-power-up: boolean. Indicates that an implementation can
 115           skip powering up the trace unit. TRCPDCR.PU does not have to be set
 116           on Qualcomm Technologies Inc. systems since ETMs are in the same power
 117           domain as their CPU cores. This property is required to identify such
 118           systems with hardware errata where the CPU watchdog counter is stopped
 119           when TRCPDCR.PU is set.
 120
 121 * Optional property for TMC:
 122
 123         * arm,buffer-size: size of contiguous buffer space for TMC ETR
 124           (embedded trace router). This property is obsolete. The buffer size
 125           can be configured dynamically via buffer_size property in sysfs.
 126
 127         * arm,scatter-gather: boolean. Indicates that the TMC-ETR can safely
 128           use the SG mode on this system.
 129
 130 * Optional property for CATU :
 131         * interrupts : Exactly one SPI may be listed for reporting the address
 132           error
 133
 134 * Optional property for configurable replicators:
 135
 136         * qcom,replicator-loses-context: boolean. Indicates that the replicator
 137           will lose register context when AMBA clock is removed which is observed
 138           in some replicator designs.
 139
 140 Graph bindings for Coresight
 141 -------------------------------
 142
 143 Coresight components are interconnected to create a data path for the flow of
 144 trace data generated from the "sources" to their collection points "sink".
 145 Each coresight component must describe the "input" and "output" connections.
 146 The connections must be described via generic DT graph bindings as described
 147 by the "bindings/graph.txt", where each "port" along with an "endpoint"
 148 component represents a hardware port and the connection.
 149
 150  * All output ports must be listed inside a child node named "out-ports"
 151  * All input ports must be listed inside a child node named "in-ports".
 152  * Port address must match the hardware port number.
 153
 154 Example:
 155
 156 1. Sinks
 157         etb@20010000 {
 158                 compatible = "arm,coresight-etb10", "arm,primecell";
 159                 reg = <0 0x20010000 0 0x1000>;
 160
 161                 clocks = <&oscclk6a>;
 162                 clock-names = "apb_pclk";
 163                 in-ports {
 164                         port {
 165                                 etb_in_port: endpoint@0 {
 166                                         remote-endpoint = <&replicator_out_port0>;
 167                                 };
 168                         };
 169                 };
 170         };
 171
 172         tpiu@20030000 {
 173                 compatible = "arm,coresight-tpiu", "arm,primecell";
 174                 reg = <0 0x20030000 0 0x1000>;
 175
 176                 clocks = <&oscclk6a>;
 177                 clock-names = "apb_pclk";
 178                 in-ports {
 179                         port {
 180                                 tpiu_in_port: endpoint@0 {
 181                                         remote-endpoint = <&replicator_out_port1>;
 182                                 };
 183                         };
 184                 };
 185         };
 186
 187         etr@20070000 {
 188                 compatible = "arm,coresight-tmc", "arm,primecell";
 189                 reg = <0 0x20070000 0 0x1000>;
 190
 191                 clocks = <&oscclk6a>;
 192                 clock-names = "apb_pclk";
 193                 in-ports {
 194                         port {
 195                                 etr_in_port: endpoint {
 196                                         remote-endpoint = <&replicator2_out_port0>;
 197                                 };
 198                         };
 199                 };
 200
 201                 out-ports {
 202                         port {
 203                                 etr_out_port: endpoint {
 204                                         remote-endpoint = <&catu_in_port>;
 205                                 };
 206                         };
 207                 };
 208         };
 209
 210 2. Links
 211         replicator {
 212                 /* non-configurable replicators don't show up on the
 213                  * AMBA bus.  As such no need to add "arm,primecell".
 214                  */
 215                 compatible = "arm,coresight-static-replicator";
 216
 217                 out-ports {
 218                         #address-cells = <1>;
 219                         #size-cells = <0>;
 220
 221                         /* replicator output ports */
 222                         port@0 {
 223                                 reg = <0>;
 224                                 replicator_out_port0: endpoint {
 225                                         remote-endpoint = <&etb_in_port>;
 226                                 };
 227                         };
 228
 229                         port@1 {
 230                                 reg = <1>;
 231                                 replicator_out_port1: endpoint {
 232                                         remote-endpoint = <&tpiu_in_port>;
 233                                 };
 234                         };
 235                 };
 236
 237                 in-ports {
 238                         port {
 239                                 replicator_in_port0: endpoint {
 240                                         remote-endpoint = <&funnel_out_port0>;
 241                                 };
 242                         };
 243                 };
 244         };
 245
 246         funnel {
 247                 /*
 248                  * non-configurable funnel don't show up on the AMBA
 249                  * bus.  As such no need to add "arm,primecell".
 250                  */
 251                 compatible = "arm,coresight-static-funnel";
 252                 clocks = <&crg_ctrl HI3660_PCLK>;
 253                 clock-names = "apb_pclk";
 254
 255                 out-ports {
 256                         port {
 257                                 combo_funnel_out: endpoint {
 258                                         remote-endpoint = <&top_funnel_in>;
 259                                 };
 260                         };
 261                 };
 262
 263                 in-ports {
 264                         #address-cells = <1>;
 265                         #size-cells = <0>;
 266
 267                         port@0 {
 268                                 reg = <0>;
 269                                 combo_funnel_in0: endpoint {
 270                                         remote-endpoint = <&cluster0_etf_out>;
 271                                 };
 272                         };
 273
 274                         port@1 {
 275                                 reg = <1>;
 276                                 combo_funnel_in1: endpoint {
 277                                         remote-endpoint = <&cluster1_etf_out>;
 278                                 };
 279                         };
 280                 };
 281         };
 282
 283         funnel@20040000 {
 284                 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
 285                 reg = <0 0x20040000 0 0x1000>;
 286
 287                 clocks = <&oscclk6a>;
 288                 clock-names = "apb_pclk";
 289                 out-ports {
 290                         port {
 291                                 funnel_out_port0: endpoint {
 292                                         remote-endpoint =
 293                                                         <&replicator_in_port0>;
 294                                 };
 295                         };
 296                 };
 297
 298                 in-ports {
 299                         #address-cells = <1>;
 300                         #size-cells = <0>;
 301
 302                         port@0 {
 303                                 reg = <0>;
 304                                 funnel_in_port0: endpoint {
 305                                         remote-endpoint = <&ptm0_out_port>;
 306                                 };
 307                         };
 308
 309                         port@1 {
 310                                 reg = <1>;
 311                                 funnel_in_port1: endpoint {
 312                                         remote-endpoint = <&ptm1_out_port>;
 313                                 };
 314                         };
 315
 316                         port@2 {
 317                                 reg = <2>;
 318                                 funnel_in_port2: endpoint {
 319                                         remote-endpoint = <&etm0_out_port>;
 320                                 };
 321                         };
 322
 323                 };
 324         };
 325
 326 3. Sources
 327         ptm@2201c000 {
 328                 compatible = "arm,coresight-etm3x", "arm,primecell";
 329                 reg = <0 0x2201c000 0 0x1000>;
 330
 331                 cpu = <&cpu0>;
 332                 clocks = <&oscclk6a>;
 333                 clock-names = "apb_pclk";
 334                 out-ports {
 335                         port {
 336                                 ptm0_out_port: endpoint {
 337                                         remote-endpoint = <&funnel_in_port0>;
 338                                 };
 339                         };
 340                 };
 341         };
 342
 343         ptm@2201d000 {
 344                 compatible = "arm,coresight-etm3x", "arm,primecell";
 345                 reg = <0 0x2201d000 0 0x1000>;
 346
 347                 cpu = <&cpu1>;
 348                 clocks = <&oscclk6a>;
 349                 clock-names = "apb_pclk";
 350                 out-ports {
 351                         port {
 352                                 ptm1_out_port: endpoint {
 353                                         remote-endpoint = <&funnel_in_port1>;
 354                                 };
 355                         };
 356                 };
 357         };
 358
 359 4. STM
 360         stm@20100000 {
 361                 compatible = "arm,coresight-stm", "arm,primecell";
 362                 reg = <0 0x20100000 0 0x1000>,
 363                       <0 0x28000000 0 0x180000>;
 364                 reg-names = "stm-base", "stm-stimulus-base";
 365
 366                 clocks = <&soc_smc50mhz>;
 367                 clock-names = "apb_pclk";
 368                 out-ports {
 369                         port {
 370                                 stm_out_port: endpoint {
 371                                         remote-endpoint = <&main_funnel_in_port2>;
 372                                 };
 373                         };
 374                 };
 375         };
 376
 377 5. CATU
 378
 379         catu@207e0000 {
 380                 compatible = "arm,coresight-catu", "arm,primecell";
 381                 reg = <0 0x207e0000 0 0x1000>;
 382
 383                 clocks = <&oscclk6a>;
 384                 clock-names = "apb_pclk";
 385
 386                 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 387                 in-ports {
 388                         port {
 389                                 catu_in_port: endpoint {
 390                                         remote-endpoint = <&etr_out_port>;
 391                                 };
 392                         };
 393                 };
 394         };
 395
 396 [1]. There is currently two version of STM: STM32 and STM500.  Both
 397 have the same HW interface and as such don't need an explicit binding name.