3 Chipid required properties:
4 - compatible: Should be "atmel,sama5d2-chipid"
5 - reg : Should contain registers location and length
7 PIT Timer required properties:
8 - compatible: Should be "atmel,at91sam9260-pit"
9 - reg: Should contain registers location and length
10 - interrupts: Should contain interrupt for the PIT which is the IRQ line
11 shared across all System Controller members.
13 PIT64B Timer required properties:
14 - compatible: Should be "microchip,sam9x60-pit64b"
15 - reg: Should contain registers location and length
16 - interrupts: Should contain interrupt for PIT64B timer
17 - clocks: Should contain the available clock sources for PIT64B timer.
19 System Timer (ST) required properties:
20 - compatible: Should be "atmel,at91rm9200-st", "syscon", "simple-mfd"
21 - reg: Should contain registers location and length
22 - interrupts: Should contain interrupt for the ST which is the IRQ line
23 shared across all System Controller members.
24 - clocks: phandle to input clock.
26 - watchdog: compatible should be "atmel,at91rm9200-wdt"
28 RSTC Reset Controller required properties:
29 - compatible: Should be "atmel,<chip>-rstc".
30 <chip> can be "at91sam9260", "at91sam9g45", "sama5d3" or "samx7"
31 it also can be "microchip,sam9x60-rstc"
32 - reg: Should contain registers location and length
33 - clocks: phandle to input clock.
38 compatible = "atmel,at91sam9260-rstc";
39 reg = <0xfffffd00 0x10>;
43 RAMC SDRAM/DDR Controller required properties:
44 - compatible: Should be "atmel,at91rm9200-sdramc", "syscon"
45 "atmel,at91sam9260-sdramc",
46 "atmel,at91sam9g45-ddramc",
47 "atmel,sama5d3-ddramc",
48 - reg: Should contain registers location and length
52 ramc0: ramc@ffffe800 {
53 compatible = "atmel,at91sam9g45-ddramc";
54 reg = <0xffffe800 0x200>;
57 SHDWC Shutdown Controller
60 - compatible: Should be "atmel,<chip>-shdwc".
61 <chip> can be "at91sam9260", "at91sam9rl" or "at91sam9x5".
62 - reg: Should contain registers location and length
63 - clocks: phandle to input clock.
66 - atmel,wakeup-mode: String, operation mode of the wakeup mode.
67 Supported values are: "none", "high", "low", "any".
68 - atmel,wakeup-counter: Counter on Wake-up 0 (between 0x0 and 0xf).
70 optional at91sam9260 properties:
71 - atmel,wakeup-rtt-timer: boolean to enable Real-time Timer Wake-up.
73 optional at91sam9rl properties:
74 - atmel,wakeup-rtc-timer: boolean to enable Real-time Clock Wake-up.
75 - atmel,wakeup-rtt-timer: boolean to enable Real-time Timer Wake-up.
77 optional at91sam9x5 properties:
78 - atmel,wakeup-rtc-timer: boolean to enable Real-time Clock Wake-up.
83 compatible = "atmel,at91sam9260-shdwc";
84 reg = <0xfffffd10 0x10>;
88 SHDWC SAMA5D2-Compatible Shutdown Controller
93 - compatible: should be "atmel,sama5d2-shdwc" or "microchip,sam9x60-shdwc".
94 - reg: should contain registers location and length
95 - clocks: phandle to input clock.
96 - #address-cells: should be one. The cell is the wake-up input index.
97 - #size-cells: should be zero.
101 - debounce-delay-us: minimum wake-up inputs debouncer period in
102 microseconds. It's usually a board-related property.
103 - atmel,wakeup-rtc-timer: boolean to enable Real-Time Clock wake-up.
105 optional microchip,sam9x60-shdwc properties:
106 - atmel,wakeup-rtt-timer: boolean to enable Real-time Timer Wake-up.
108 The node contains child nodes for each wake-up input that the platform uses.
112 Wake-up input nodes are usually described in the "board" part of the Device
113 Tree. Note also that input 0 is linked to the wake-up pin and is frequently
117 - reg: should contain the wake-up input index [0 - 15].
120 - atmel,wakeup-active-high: boolean, the corresponding wake-up input described
121 by the child, forces the wake-up of the core power supply on a high level.
122 The default is to be active low.
128 compatible = "atmel,sama5d2-shdwc";
129 reg = <0xf8048010 0x10>;
131 #address-cells = <1>;
133 atmel,wakeup-rtc-timer;
138 debounce-delay-us = <976>;
146 atmel,wakeup-active-high;
150 Special Function Registers (SFR)
152 Special Function Registers (SFR) manage specific aspects of the integrated
153 memory, bridge implementations, processor and other functionality not controlled
157 - compatible: Should be "atmel,<chip>-sfr", "syscon" or
158 "atmel,<chip>-sfrbu", "syscon"
159 <chip> can be "sama5d3", "sama5d4" or "sama5d2".
160 It also can be "microchip,sam9x60-sfr", "syscon".
161 - reg: Should contain registers location and length
164 compatible = "atmel,sama5d3-sfr", "syscon";
165 reg = <0xf0038000 0x60>;
168 Security Module (SECUMOD)
170 The Security Module macrocell provides all necessary secure functions to avoid
171 voltage, temperature, frequency and mechanical attacks on the chip. It also
172 embeds secure memories that can be scrambled.
174 The Security Module also offers the PIOBU pins which can be used as GPIO pins.
175 Note that they maintain their voltage during Backup/Self-refresh.
178 - compatible: Should be "atmel,<chip>-secumod", "syscon".
179 <chip> can be "sama5d2".
180 - reg: Should contain registers location and length
181 - gpio-controller: Marks the port as GPIO controller.
182 - #gpio-cells: There are 2. The pin number is the
183 first, the second represents additional
184 parameters such as GPIO_ACTIVE_HIGH/LOW.
188 compatible = "atmel,sama5d2-secumod", "syscon";
189 reg = <0xfc040000 0x100>;