1 What: /sys/devices/platform/<platform>/etr3
4 Contact: "Tomas Winkler" <tomas.winkler@intel.com>
6 The file exposes "Extended Test Mode Register 3" global
7 reset bits. The bits are used during an Intel platform
8 manufacturing process to indicate that consequent reset
9 of the platform is a "global reset". This type of reset
10 is required in order for manufacturing configurations
13 Display global reset setting bits for PMC.
14 * bit 31 - global reset is locked
15 * bit 20 - global reset is set
16 Writing bit 20 value to the etr3 will induce
17 a platform "global reset" upon consequent platform reset,
18 in case the register is not locked.
19 The "global reset bit" should be locked on a production
20 system and the file is in read-only mode.