1 What: /sys/bus/cxl/devices/memX/firmware_version
4 Contact: linux-cxl@vger.kernel.org
6 (RO) "FW Revision" string as reported by the Identify
7 Memory Device Output Payload in the CXL-2.0
10 What: /sys/bus/cxl/devices/memX/ram/size
13 Contact: linux-cxl@vger.kernel.org
15 (RO) "Volatile Only Capacity" as bytes. Represents the
16 identically named field in the Identify Memory Device Output
17 Payload in the CXL-2.0 specification.
19 What: /sys/bus/cxl/devices/memX/pmem/size
22 Contact: linux-cxl@vger.kernel.org
24 (RO) "Persistent Only Capacity" as bytes. Represents the
25 identically named field in the Identify Memory Device Output
26 Payload in the CXL-2.0 specification.
28 What: /sys/bus/cxl/devices/*/devtype
31 Contact: linux-cxl@vger.kernel.org
33 CXL device objects export the devtype attribute which mirrors
34 the same value communicated in the DEVTYPE environment variable
35 for uevents for devices on the "cxl" bus.
37 What: /sys/bus/cxl/devices/portX/uport
40 Contact: linux-cxl@vger.kernel.org
42 CXL port objects are enumerated from either a platform firmware
43 device (ACPI0017 and ACPI0016) or PCIe switch upstream port with
44 CXL component registers. The 'uport' symlink connects the CXL
45 portX object to the device that published the CXL port
48 What: /sys/bus/cxl/devices/portX/dportY
51 Contact: linux-cxl@vger.kernel.org
53 CXL port objects are enumerated from either a platform firmware
54 device (ACPI0017 and ACPI0016) or PCIe switch upstream port with
55 CXL component registers. The 'dportY' symlink identifies one or
56 more downstream ports that the upstream port may target in its
57 decode of CXL memory resources. The 'Y' integer reflects the
58 hardware port unique-id used in the hardware decoder target
61 What: /sys/bus/cxl/devices/decoderX.Y
64 Contact: linux-cxl@vger.kernel.org
66 CXL decoder objects are enumerated from either a platform
67 firmware description, or a CXL HDM decoder register set in a
68 PCIe device (see CXL 2.0 section 8.2.5.12 CXL HDM Decoder
69 Capability Structure). The 'X' in decoderX.Y represents the
70 cxl_port container of this decoder, and 'Y' represents the
71 instance id of a given decoder resource.
73 What: /sys/bus/cxl/devices/decoderX.Y/{start,size}
76 Contact: linux-cxl@vger.kernel.org
78 The 'start' and 'size' attributes together convey the physical
79 address base and number of bytes mapped in the decoder's decode
80 window. For decoders of devtype "cxl_decoder_root" the address
81 range is fixed. For decoders of devtype "cxl_decoder_switch" the
82 address is bounded by the decode range of the cxl_port ancestor
83 of the decoder's cxl_port, and dynamically updates based on the
84 active memory regions in that address space.
86 What: /sys/bus/cxl/devices/decoderX.Y/locked
89 Contact: linux-cxl@vger.kernel.org
91 CXL HDM decoders have the capability to lock the configuration
92 until the next device reset. For decoders of devtype
93 "cxl_decoder_root" there is no standard facility to unlock them.
94 For decoders of devtype "cxl_decoder_switch" a secondary bus
95 reset, of the PCIe bridge that provides the bus for this
96 decoders uport, unlocks / resets the decoder.
98 What: /sys/bus/cxl/devices/decoderX.Y/target_list
101 Contact: linux-cxl@vger.kernel.org
103 Display a comma separated list of the current decoder target
104 configuration. The list is ordered by the current configured
105 interleave order of the decoder's dport instances. Each entry in
106 the list is a dport id.
108 What: /sys/bus/cxl/devices/decoderX.Y/cap_{pmem,ram,type2,type3}
111 Contact: linux-cxl@vger.kernel.org
113 When a CXL decoder is of devtype "cxl_decoder_root", it
114 represents a fixed memory window identified by platform
115 firmware. A fixed window may only support a subset of memory
116 types. The 'cap_*' attributes indicate whether persistent
117 memory, volatile memory, accelerator memory, and / or expander
118 memory may be mapped behind this decoder's memory window.
120 What: /sys/bus/cxl/devices/decoderX.Y/target_type
123 Contact: linux-cxl@vger.kernel.org
125 When a CXL decoder is of devtype "cxl_decoder_switch", it can
126 optionally decode either accelerator memory (type-2) or expander
127 memory (type-3). The 'target_type' attribute indicates the
128 current setting which may dynamically change based on what
129 memory regions are activated in this decode hierarchy.