1 What: /sys/bus/coresight/devices/<memory_map>.etm/enable_source
4 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
5 Description: (RW) Enable/disable tracing on this specific trace entiry.
6 Enabling a source implies the source has been configured
7 properly and a sink has been identidifed for it. The path
8 of coresight components linking the source to the sink is
9 configured and managed automatically by the coresight framework.
11 What: /sys/bus/coresight/devices/<memory_map>.etm/cpu
14 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
15 Description: (R) The CPU this tracing entity is associated with.
17 What: /sys/bus/coresight/devices/<memory_map>.etm/nr_pe_cmp
20 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
21 Description: (R) Indicates the number of PE comparator inputs that are
22 available for tracing.
24 What: /sys/bus/coresight/devices/<memory_map>.etm/nr_addr_cmp
27 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
28 Description: (R) Indicates the number of address comparator pairs that are
29 available for tracing.
31 What: /sys/bus/coresight/devices/<memory_map>.etm/nr_cntr
34 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
35 Description: (R) Indicates the number of counters that are available for
38 What: /sys/bus/coresight/devices/<memory_map>.etm/nr_ext_inp
41 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
42 Description: (R) Indicates how many external inputs are implemented.
44 What: /sys/bus/coresight/devices/<memory_map>.etm/numcidc
47 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
48 Description: (R) Indicates the number of Context ID comparators that are
49 available for tracing.
51 What: /sys/bus/coresight/devices/<memory_map>.etm/numvmidc
54 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
55 Description: (R) Indicates the number of VMID comparators that are available
58 What: /sys/bus/coresight/devices/<memory_map>.etm/nrseqstate
61 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
62 Description: (R) Indicates the number of sequencer states that are
65 What: /sys/bus/coresight/devices/<memory_map>.etm/nr_resource
68 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
69 Description: (R) Indicates the number of resource selection pairs that are
70 available for tracing.
72 What: /sys/bus/coresight/devices/<memory_map>.etm/nr_ss_cmp
75 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
76 Description: (R) Indicates the number of single-shot comparator controls that
77 are available for tracing.
79 What: /sys/bus/coresight/devices/<memory_map>.etm/reset
82 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
83 Description: (W) Cancels all configuration on a trace unit and set it back
84 to its boot configuration.
86 What: /sys/bus/coresight/devices/<memory_map>.etm/mode
89 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
90 Description: (RW) Controls various modes supported by this ETM, for example
91 P0 instruction tracing, branch broadcast, cycle counting and
94 What: /sys/bus/coresight/devices/<memory_map>.etm/pe
97 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
98 Description: (RW) Controls which PE to trace.
100 What: /sys/bus/coresight/devices/<memory_map>.etm/event
103 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
104 Description: (RW) Controls the tracing of arbitrary events from bank 0 to 3.
106 What: /sys/bus/coresight/devices/<memory_map>.etm/event_instren
109 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
110 Description: (RW) Controls the behavior of the events in bank 0 to 3.
112 What: /sys/bus/coresight/devices/<memory_map>.etm/event_ts
115 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
116 Description: (RW) Controls the insertion of global timestamps in the trace
119 What: /sys/bus/coresight/devices/<memory_map>.etm/syncfreq
122 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
123 Description: (RW) Controls how often trace synchronization requests occur.
125 What: /sys/bus/coresight/devices/<memory_map>.etm/cyc_threshold
128 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
129 Description: (RW) Sets the threshold value for cycle counting.
131 What: /sys/bus/coresight/devices/<memory_map>.etm/bb_ctrl
134 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
135 Description: (RW) Controls which regions in the memory map are enabled to
136 use branch broadcasting.
138 What: /sys/bus/coresight/devices/<memory_map>.etm/event_vinst
141 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
142 Description: (RW) Controls instruction trace filtering.
144 What: /sys/bus/coresight/devices/<memory_map>.etm/s_exlevel_vinst
147 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
148 Description: (RW) In Secure state, each bit controls whether instruction
149 tracing is enabled for the corresponding exception level.
151 What: /sys/bus/coresight/devices/<memory_map>.etm/ns_exlevel_vinst
154 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
155 Description: (RW) In non-secure state, each bit controls whether instruction
156 tracing is enabled for the corresponding exception level.
158 What: /sys/bus/coresight/devices/<memory_map>.etm/addr_idx
161 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
162 Description: (RW) Select which address comparator or pair (of comparators) to
165 What: /sys/bus/coresight/devices/<memory_map>.etm/addr_instdatatype
168 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
169 Description: (RW) Controls what type of comparison the trace unit performs.
171 What: /sys/bus/coresight/devices/<memory_map>.etm/addr_single
174 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
175 Description: (RW) Used to setup single address comparator values.
177 What: /sys/bus/coresight/devices/<memory_map>.etm/addr_range
180 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
181 Description: (RW) Used to setup address range comparator values.
183 What: /sys/bus/coresight/devices/<memory_map>.etm/seq_idx
186 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
187 Description: (RW) Select which sequensor.
189 What: /sys/bus/coresight/devices/<memory_map>.etm/seq_state
192 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
193 Description: (RW) Use this to set, or read, the sequencer state.
195 What: /sys/bus/coresight/devices/<memory_map>.etm/seq_event
198 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
199 Description: (RW) Moves the sequencer state to a specific state.
201 What: /sys/bus/coresight/devices/<memory_map>.etm/seq_reset_event
204 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
205 Description: (RW) Moves the sequencer to state 0 when a programmed event
208 What: /sys/bus/coresight/devices/<memory_map>.etm/cntr_idx
211 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
212 Description: (RW) Select which counter unit to work with.
214 What: /sys/bus/coresight/devices/<memory_map>.etm/cntrldvr
217 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
218 Description: (RW) This sets or returns the reload count value of the
221 What: /sys/bus/coresight/devices/<memory_map>.etm/cntr_val
224 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
225 Description: (RW) This sets or returns the current count value of the
228 What: /sys/bus/coresight/devices/<memory_map>.etm/cntr_ctrl
231 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
232 Description: (RW) Controls the operation of the selected counter.
234 What: /sys/bus/coresight/devices/<memory_map>.etm/res_idx
237 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
238 Description: (RW) Select which resource selection unit to work with.
240 What: /sys/bus/coresight/devices/<memory_map>.etm/res_ctrl
243 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
244 Description: (RW) Controls the selection of the resources in the trace unit.